AMIS-53050 Datasheet, PDF (63/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Table 41: CDR OptionsA - 0X1F [31]
Bit Name
State
11
7,6 DR Clamp<1>
10
01
00
11
5,4 Channel clamp
10
01
00
11
3,2 Activity check <1> 10
01
00
1
1
FPA enable
0
1
0
FM mode
0
Comment
1/64
1/32
The clamp restricts the clock recovery PLL to +- the fraction selected
1/16
of the frequency selected by the BaudCLK which prevents clock
wandering between data packets
1/8
+-150
+-100
+-50
The clamp restricts the PLL detector to only lock on signals that are
within the specified window, centered +-500kHz of the IF frequency
+-16
Reset after 16 bit times of no activity
Reset after 8 bit times of no activity
Reset after 4 bit times of no activity
Activity check disabled, clock recovery will always run
The CDR circuit will perform fast phase alignment
CDR always running
PLL
FFT
CDR Options B
The sample clock values are written from ROM with the discrete data rate selected. The sample rate should be as fast as possible
without exceeding 400 samples per bit time.
Table 42: CDR OptionsB - 0X20 [32]
Bit Name
State
1
7
CDR reset
0
6
NU
5
NU
Comment
CDR is held reset
4
NU
3:0 ^{Sample clock}
1011
1010
1001
1000
0111
0110
0101
0100
0011
0010
0001
0000
45kHz
90kHz
187.5kHz
375kHz
750kHz
1.5M
3M
6M
8M
12M
16M
24M
Clock Recovery Loop Filter Setting
A program (AMIS-53CDRPLLCalc.exe available from AMIS) has been created to aid in the design of the CDR loop filter settings.
Table 43: Clock Recovery Loop Filter Setting - 0X2C [44]
Bit Name
Comment
7:0 _{CDR_CO [7:0]}
Clock recovery filter setting
AMI Semiconductor – Jan. 07, M-20639-002
63
www.amis.com