AMIS-53050 Datasheet, PDF (37/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Figure 26: Sequential Control Register Read/Write Using the 3-Wire Interface
Figure 26 is a diagram for sequential reads or writes for 3-wire control data transfer. The format of the instruction and address is
identical to that for a single read/write operation, with the address corresponding to the first register location to read or write. The first
eight bits of data transferred correspond to the address selected. The address is internally incremented after each data byte is
transferred. This task is most useful for writing to or reading from variables spanning over multiple address locations, such as the
fractional PLL word (registers 03-05).
The SSN line must be de-asserted at the completion of a sequential read/write in order for the slave SPI controller to correctly interpret
the next eight bits as a command and not data.
6.1.4. I²C Interface
The I²C interface for the AMIS-53050 is compatible with the Philip Semiconductor I²C standard, with the AMIS-53050 as the slave
device.
6.1.4.1. I2C Device Addressing
A control byte is the first byte received following the start condition from the Master device. The control byte consists of 7-bits for the
device address, and 1-bit for a read or write command. For the AMIS-53050, the device address is ‘0110100’ binary. The last bit of the
control byte defines the operation to be performed. When set to ‘1’, a read operation is selected. When set to ‘0’, a write operation is
selected. Following the start condition, the AMIS-53050 monitors the SDA bus checking the device type identifier being transmitted.
Upon receiving its device address, the AMIS-53050 outputs an acknowledge signal on the SDA line. Depending on the state of the R/W
bit, the AMIS-53050 will select a read or write operation.
AMI Semiconductor – Jan. 07, M-20639-002
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