AMIS-53050 Datasheet, PDF (85/107 Pages) AMI SEMICONDUCTOR – Frequency Agile Transceiver

AMIS-53050 Frequency Agile Transceiver
Data Sheet
Length of Packet Enable: Allows buffering of packets, also allows CRC when enabled. The number of bytes to be sent is
(N-1), where (N) corresponds to the value in the Default Length of Packet register. Note: When the default LOP or LOP value
is anything other than zero (along with the Default LOP option bit enabled), the AMIS-53050 is in Packet mode.
Use ID in RX and TX: When enabled, in receive mode the part will not output data until a valid ID is found, and in TX, the part
will automatically send preamble and chip ID before enabling the data interface.
Table 88: General OptionsA - 0X0C [12]
Bit
Name
State
1
7
Use ID in RX and TX
0
6
Length of packet
enable
1
0
1
5
CRC enable
0
4
Temperature
compensation
1
0
1
3
Pull-up disable
0
00
[2:1] POR state
01
10
11
1
0
Standby mode
0
Comment
Wake on ID in RX, send ID in TX
Enables the part to frame packets
Enables CRC (packet length must be enabled)
RF center frequency temperature compensation enabled
Temperature compensation is disabled
Pull ups on IIC clock and data and SSN pins disabled
Standby
Idle
RX
TX
Crystal only mode, system clock output active
Low-power standby mode
7.1.5. General Options B
General options B contains more option bits for the general set-up and operation of the AMIS-53050.
System Clock Output Frequency: Sets the frequency of the output clock on the SYSclk pin when enabled.
RXTX Sampling Edge: Specifies which edge of DCLK should be used to sample the RXTX pin.
Length of Packet Enable: This register defines the default LOP (register 0X31) so that the LOP does not have to be part of
the data packet. This needs to be set to the same value in both the transmitting AMIS-53050 device and the receiving
AMIS-53050 device, respectively. Note: When the default LOP or LOP value is anything other than zero (along with the
Default LOP option bit enabled), the AMIS-53050 is in Packet mode.
Data Interface Clock Frequency: Sets the clock frequency for the data interface when the AMIS-53050 is configured to be
the master of the data interface. For modes in which the AMIS-53050 does not buffer the packet, the interface speed will
always be the data rate, regardless of this setting.
Data Interface Slave/Master: Specifies whether the AMIS-53050 is the master or slave for the data interface.
4-Wire Data Interface: Enables the 4-wire SPI data interface. When low, RXTX is bi-directional.
AMI Semiconductor – Jan. 07, M-20639-002
85
www.amis.com