AK4951AEN Datasheet, PDF (96/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ Headphone Amplifier Output
FS3-0 bits
(Addr:06H, D3-0)
1011
(1)
1011
DVL7-0 bits
(Addr:13H)
18H
(2)
18H
Digital Filter Path
03H
03H
(Addr:1DH)
(3)
PMDAC bit
(Addr:00H, D2)
(4)
(5)
PMHPL/R bits
(Addr:01H, D5-4)
> 34.2ms
HPL pin
HPR pin
Figure 65. Headphone-Amp Output Sequence
Example:
PLL, Master Mode
Audio I/F Format: I2S Compatible
Sampling Frequency: 48KHz
Output Digital Volume: 0dB
PMBP bit = “0”
Programmable Filter OFF
(1) Addr:06H, Data:0BH
(2) Addr:13H, Data:18H
(3) Addr:1DH, Data:03H
(4) Addr:00H, Data:44H
Addr:01H, Data:3CH
Playback
(5) Addr:01H, Data:0CH
Addr:00H, Data:40H
<Sequence>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up the sampling frequency (FS3-0 bits). When the AK4951A is PLL mode, the Headphone
Amplifier and DAC of (4) must be powered-up in consideration of PLL lock time after the sampling
frequency is changed.
(2) Set up the digital output volume (Addr = 13H)
(3) Set up Programmable Filter Path: PFDAC1-0, ADCPF and PFSDO bits (Addr = 1DH)
(4) Power up DAC and Headphone Amplifier: PMDAC = PMHPL = PMHPR bits = “0” → “1”
When PMHPL = PMHPR bits = “1”, the charge pump circuit is powered-up. The power-up time of
Headphone Amplifier block is 34.2ms (max).
(5) Power down DAC and Headphone Amplifier: PMDAC = PMHPL = PMHPR bits = “1” → “0”
016001936-E-00
- 96 -
2016/03