AK4951AEN Datasheet, PDF (55/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
5. Example of registers set-up sequence of ALC Operation
The following registers must not be changed during ALC operation. These bits must be changed after
ALC operation is stopped by ALC bit = “0”. ALC output is “0” data until the AK4951A becomes manual
mode after writing “0” to ALC bit.
LMTH2-0, WTM1-0, RGAIN2-0, REF7-0, RFST1-0, EQFC1-0, FRATT, FRN and ALCEQN bits
Manual Mode
Example:
Recovery Waiting Period = 21.3ms@48kHz
Recovery Gain = 0.00106dB (2/fs)
Fast Recovery Gain = 0.0032dB
Maximum Gain = +30.0dB
Gain of IVOL = +30.0dB
Limiter Detection Level = 4.1dBFS
EQFC1-0 bits = “10”
ALCEQN bit = “0”
FRATT bit = “0”
FRN bit = “0”
ALC bit = “1”
WR (FRATT= “0”, FRN = “0”)
(1) Addr=09H, Data=00H
WR (EQFC1-0, WTM1-0, RFST1-0)
(2) Addr=0AH, Data=6CH
WR (REF7-0)
(3) Addr=0CH, Data=E1H
WR (IVL/R7-0)
* The value of IVOL should be
the same or smaller than REF’s
(4) Addr=0DH&0EH, Data=E1H
WR (ALCEQN = “0”, ALC = “1”, RGAIN2-0, LMTH2-0)
(5) Addr=0BH, Data=2EH
ALC Operation
WR: Write
Figure 39. Registers Set-up Sequence at ALC Operation (Recording path)
016001936-E-00
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2016/03