AK4951AEN Datasheet, PDF (92/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

2. PLL Slave Mode (BICK pin)
[AK4951A]
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D2)
LRCK pin
BICK pin
Internal Clock
(1)
(2) (3)
>2.0ms
(4)
Input
2ms(max)
Example:
Audio I/F Format : I2S Compatible (ADC & DAC)
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 48kHz
4f₍s₁₎of_{Power Supply & PDN pin = “L”  “H”}
(2)Dummy Command
Addr:05H, Data:33H
Addr:06H, Data:0BH
(3) Addr:00H, Data:40H
(5)
(4) Addr:01H, Data:04H
Figure 60. Clock Set Up Sequence (2)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 200ns or more is needed to reset the AK4951A.
(2) After Dummy Command (Addr:00H, Data:00H) input, DIF1-0, PLL3-0, and FS3-0 bits must be set
during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is
2.0ms (max) when the capacitance of an external capacitor for the VCOM and the REGFIL pin is
2.2μF each.
(4) PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (BICK pin) is
supplied. PLL lock time is 2ms (max) when BICK is a PLL reference clock.
(5) Normal operation starts after that the PLL is locked.
016001936-E-00
- 92 -
2016/03