AK4951AEN Datasheet, PDF (33/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
The ADC starts an initialization cycle if the one of PMADL or PMADR is set to “1” when both of the
PMADL and PMADR bits are “0”. The initialization cycle is set by ADRST1-0 bits (Table 18). During the
initialization cycle, the ADC digital data outputs of both channels are forced to “0” in 2's complement. The
ADC output reflects the analog input signal after the initialization cycle is finished. When using a digital
microphone (PMDML/R bits =“0” → “1”), the initialization cycle is the same as ADC’s.
Note 36. The initial data of ADC has offset data that depends on microphones and the cut-off frequency of
HPF. If this offset is not small, make initialization cycle longer by setting ADRST1-0 bits or do not
use the first data of ADC outputs.
ADRST1-0 bits
00
01
10
11
Table 18. ADC Initialization Cycle
Initialize Cycle
Cycle
fs = 8kHz
fs = 16kHz
1059/fs
132.4ms
66.2ms
267/fs
33.4ms
16.7ms
531/fs
66.4ms
33.2ms
135/fs
16.9ms
8.4ms
fs = 48kHz
22ms
5.6ms
11.1ms
2.8ms
(default)
The DAC is initialized by setting PMDAC bit “0” → “1”. The initialization cycle is 2/fs. Therefore, the DAC
outputs signals after group delay period and 2/fs when power up the device. Normally, this group delay
period or 2/fs initialization cycle mentioned above is absorbed by power-up time of amplifiers after the
DAC (Headphone-amp, Lineout-amp and SPK-amp).
016001936-E-00
- 33 -
2016/03