AK4951AEN Datasheet, PDF (19/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
Parameter
Control Interface Timing (I²C Bus)
Symbol Min. Typ. Max. Unit
SCL Clock Frequency
Bus Free Time Between Transmissions
fSCL
-
-
400 kHz
tBUF 1.3
-
-
s
Start Condition Hold Time (prior to first clock pulse)
tHD:STA 0.6
-
-
s
Clock Low Time
tLOW 1.3
-
-
s
Clock High Time
tHIGH 0.6
-
-
s
Setup Time for Repeated Start Condition
tSU:STA 0.6
-
-
s
SDA Hold Time from SCL Falling (Note 26)
tHD:DAT 0
-
-
s
SDA Setup Time from SCL Rising
tSU:DAT 0.1
-
-
s
Rise Time of Both SDA and SCL Lines
tR
-
-
0.3 s
Fall Time of Both SDA and SCL Lines
tF
-
-
0.3 s
Setup Time for Stop Condition
tSU:STO 0.6
-
-
s
Capacitive Load on Bus
Cb
-
-
400 pF
Pulse Width of Spike Noise Suppressed by Input Filter
tSP
0
-
50 ns
Power-down & Reset Timing
PDN Accept Pulse Width
PDN Reject Pulse Width
(Note 29)
(Note 29)
tAPD 200
-
tRPD
-
-
-
ns
50 ns
PMADL or PMADR “” to SDTO valid (Note 30)
ADRST1-0 bits =“00”
ADRST1-0 bits =“01”
ADRST1-0 bits =“10”
ADRST1-0 bits =“11”
tPDV
tPDV
tPDV
tPDV
- 1059 - 1/fs
-
267
- 1/fs
-
531
- 1/fs
-
135
- 1/fs
VCOM Voltage
Rising Time
(Note 31)
tRVCM
-
0.6 2.0 ms
Note 25. I²C Bus is a trademark of NXP B.V.
Note 26. Data must be held for sufficient time to bridge the 300ns transition time of SCL.
Note 27. CCLK rising edge must not occur at the same time as CSN edge.
Note 28. It is the time of 10% potential change of the CDTIO pin when R_L = 1kΩ (pull-up or TVDD).
Note 29. The AK4951A can be reset by the PDN pin = “L”. The PDN pin must be held “L” for more than
200ns for a certain reset. The AK4951A is not reset by the “L” pulse less than 50ns.
Note 30. This is the count of LRCK “↑” from the PMADL or PMADR bit = “1”.
Note 31. All analog blocks including PLL block are powered up after the VCOM voltage (VCOM pin) rises
up. An external capacitor of the VCOM pin is 2.2F and the REGFIL pin is 2.2F. The
capacitance variation should be ±50%.
016001936-E-00
- 19 -
2016/03