AK4951AEN Datasheet, PDF (30/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4951A becomes EXT mode. Master clock can be input to the internal ADC
and DAC directly from the MCKI pin without internal PLL circuit operation. This mode is compatible with
I/F of a normal audio CODEC. The external clocks required to operate this mode are MCKI (256fs, 384fs,
512fs or 1024fs), LRCK (fs) and BICK (32fs). The master clock (MCKI) must be synchronized with
LRCK. The phase between these clocks is not important. The input frequency of MCKI is selected by
CM1-0 bits (Table 11) and the sampling frequency is selected by FS3-0 bits (Table 12).
Mode
0
1
2
3
Table 11. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
CM1 bit CM0 bit MCKI Input Frequency Sampling Frequency Range
0
0
256fs
8kHz ≤ fs ≤ 48kHz
(default)
0
1
384fs
8kHz ≤ fs ≤ 48kHz
1
0
512fs
8kHz ≤ fs ≤ 48kHz
1
1
1024fs
8kHz ≤ fs ≤ 24kHz
Mode FS3 bit
0
0
1
0
2
0
5
0
7
0
9
1
10
1
11
1
15
1
Others
(N/A: Not Available)
Table 12. Setting of Sampling Frequency
FS2 bit FS1 bit FS0 bit Sampling Frequency
0
0
0
8kHz mode
0
0
1
12kHz mode
0
1
0
16kHz mode
1
0
1
11.025kHz mode
1
1
1
22.05kHz mode
0
0
1
24kHz mode
0
1
0
32kHz mode
0
1
1
48kHz mode
1
1
1
44.1kHz mode
Others
N/A
(default)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to
out-of-band noise. The out-of-band noise can be reduced by using higher frequency of the master clock.
The S/N of the DAC output through HPL/HPR pins is shown in Table 13.
Table 13. Relationship between MCKI and S/N of HPL/HPR pins
MCKI
S/N (fs=8kHz, 20kHzLPF + A-weighted)
256fs
82dB
384fs
82dB
512fs
95dB
1024fs
97dB
AK4951A
MCKI
BICK
LRCK
SDTO
SDTI
256fs, 384fs,
512fs or 1024fs
 32fs
1fs
DSP or P
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 17. EXT Slave Mode
016001936-E-00
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2016/03