AK4951AEN Datasheet, PDF (64/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ Stereo Line Output (LOUT/ROUT pin, LOSEL bit = “1”)
When LOSEL bit is set to “1”, L and R channel signals of DAC are output in single-ended format via LOUT
and ROUT pins. The stereo line output is valid at SVDD = 2.8~3.5V. The same voltage as AVDD must be
supplied to the stereo lineout. When DACL bit is “0” at LOSEL = PMSL = SLPSN bits = “1”, output signals
are muted and LOUT and ROUT pins output common voltage. The load impedance is 10k (min.). When
PMSL bit = “0” at LOSEL = SLPSN bits = “1”, the stereo line output enters power-down mode and the
output is pulled-down to VSS3 by 100k (typ). Pop noise at power-up/down can be reduced by changing
PMSL bit when SLPSN bit = “0” at LOSEL bit = “1”. In this case, output signal line should be pulled-down
to VSS by 22k after AC coupled as Figure 45. Rise/Fall time is 300ms (max) when C=1F and
R_L=10k. When LOSEL = PMSL = SLPSN bits = “1”, stereo line output is in normal operation.
LVCM1-0 bits set the gain of stereo line output.
The DAC output signal cannot be output from stereo line out and headphone amplifier at the same time.
When the DAC output signal is output from stereo line out, the headphone amplifier should be powered
down (PMHPL=PMHPR bits=“0”).
“DACL bit” “LVCM1-0 bits”
DAC Lch
DAC Rch
LOUT pin
ROUT pin
“BEEPS bit”
BEEP-amp
Figure 44. Stereo Line Output
PMSL bit
0
1
Table 58. Stereo Line Output Mode Select
SLPSN bit
Mode
LOUT/ROUT pins
0
Power Down
Fall-down to VSS3
1
Power Down
Pull-down to VSS3
0
Power Save Rise up to Common Voltage
1
Normal
Operation
Normal Operation
(default)
Table 59. Stereo Lineout Volume Setting
LVCM1-0 bits
SVDD
(=AVDD)
Gain
Common Voltage
(typ)
00
2.8 ~ 3.6V 0dB
1.3V
01
3.0 ~ 3.6V +2dB
1.5V
(default)
10
2.8 ~ 3.6V +2dB
1.3V
11
3.0 ~ 3.6V +4dB
1.5V
016001936-E-00
- 64 -
2016/03