AK4951AEN Datasheet, PDF (24/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
9. Functional Descriptions
■ System Clock
There are the following four clock modes to interface with external devices (Table 2, Table 3).
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: BICK pin)
EXT Slave Mode
EXT Master Mode
(x: Do not care)
Table 2. Clock Mode Setting
PMPLL bit
M/S bit
1
1
1
0
0
0
0
1
PLL3-0 bits
Table 5
Table 5
x
x
Figure
Figure 15
Figure 16
Figure 17
Figure 18
Table 3. Clock pins state in Clock Mode
Mode
MCKI pin
BICK pin
LRCK pin
PLL Master Mode
Input Frequency of Table 5
Output
Output
(Selected by PLL3-0 bits) (Selected by BCKO bit) (1fs)
PLL Slave Mode
(PLL Reference Clock: BICK pin)
GND
Input
Input
(Selected by PLL3-0 bits) (1fs)
EXT Slave Mode
EXT Master Mode
Input Frequency of Table 11
(Selected by CM1-0 bits)
Input Frequency of Table 14
(Selected by CM1-0 bits)
Input
( 32fs)
Output
(Selected by BCKO bit)
Input
(1fs)
Output
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave
mode. When the AK4951A is in power-down mode (PDN pin = “L”) and when exits reset state, the
AK4951A is in slave mode. After exiting reset state, the AK4951A goes to master mode by changing M/S
bit to “1”.
When the AK4951A is in master mode, the LRCK and BICK pins are a floating state until M/S bit becomes
“1”. The LRCK and BICK pins of the AK4951A must be pulled-down or pulled-up by a resistor (about
100k) externally to avoid the floating state.
Table 4. Select Master/Slave Mode
M/S bit
Mode
0
Slave Mode (default)
1
Master Mode
016001936-E-00
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2016/03