AK4951AEN Datasheet, PDF (91/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
11. Control Sequence
■ Clock Set Up
When ADC, DAC or Programmable Filter is powered-up, the clocks must be supplied. Turn off the power
management bits first when switching the clock. The power management bits should be turned on after
the clock is stabilized.
1. PLL Master Mode
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D2)
MCKI pin
M/S bit
(Addr:01H, D3)
BICK pin
LRCK pin
(1)
(2) (3)
>2.0ms
(4)
Input
5ms(max)
(5)
Output
Example:
Audio I/F Format: I2S Compatible (ADC & DAC)
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 12MHz
Sampling Frequency: 48kHz
(1) Power Supply & PDN pin = “L”  “H”
(2)Dummy Command
Addr:01H, Data:08H
Addr:05H, Data:6BH
Addr:06H, Data:0BH
(3)Addr:00H, Data:40H
(4)Addr:01H, Data:0CH
BICK and LRCK output
Figure 59. Clock Set Up Sequence (1)
<Sequence>
(1) After Power Up: PDN pin “L” → “H”
“L” time of 200ns or more is needed to reset the AK4951A.
(2) After Dummy Command (Addr:00H, Data:00H) input, DIF1-0, PLL3-0, FS3-0, BCKO and M/S bits
must be set during this period.
(3) Power Up VCOM and Regulator: PMVCM bit = “0” → “1”
VCOM and Regulator must first be powered-up before the other block operates. Power up time is
2.0ms (max) when the capacitance of an external capacitor for the VCOM and the REGFIL pin is
2.2μF each.
(4) PLL starts after PMPLL bit changes from “0” to “1” and MCKI is supplied from an external source,
and PLL lock time is 5ms (max)
(5) The AK4951A starts to output the LRCK and BICK clocks after the PLL became stable. Then
normal operation starts.
016001936-E-00
- 91 -
2016/03