AK4951AEN Datasheet, PDF (50/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ ALC Operation
The ALC (Automatic Level Control) is operated by ALC block. When ADCPF bit is “1”, the ALC circuit
operates for recording path, and the ALC circuit operates for playback path when ADCPF bit is “0”. ALC
bit controls ON/OFF of ALC operation.
The ALC block consists of these blocks shown below. The ALC limiter detection level is monitored at the
level detection2 block after EQ block. The level detection1 block also monitors clipping detection level
(+0.53dBFS).
Input
ALC
Control
Volume
Level
Detection2
EQ
Level
Detection1
Output
Figure 37. ALC Block
The polar (fc₁) and the zero point (fs₂) frequencies of EQ block are set by EQFC1-0 bits. Set ALCEQ bits
according to the sampling frequency. When ALCEQ bit is OFF (ALCEQ bit = “1”), the level detection is not
executed on this block.
Table 34. ALCEQ Frequency Setting
EQFC1-0 Sampling Frequency
Polar Frequency
Zero-point Frequency
bits
Range
(fc₁)
(fc₂)
00
8kHz ≤ fs ≤ 12kHz
150Hz @ fs=12kHz
100Hz @ fs=12kHz
01
12kHz < fs ≤ 24kHz
150Hz @ fs=24kHz
100Hz @ fs=24kHz
10
24kHz < fs ≤ 48kHz
150Hz @ fs=48kHz
100Hz @ fs=48kHz
11
N/A
(N/A: Not available)
(default)
[ALCEQ: First order zero pole high pass filter]
Gain
[dB]
0dB
-3.5dB
100Hz
(fc₂)
150Hz
(fc₁)
Frequency
[Hz]
Note 39. Black: Diagrammatic Line, Red: Actual Curve
Figure 38. ALCEQ Frequency Response (fs = 48kHz)
016001936-E-00
- 50 -
2016/03