AK4951AEN Datasheet, PDF (69/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
2. READ Operations
Set the R/W bit = “1” for the READ operation of the AK4951A. After transmission of data, the master can
read the next address’s data by generating an acknowledge instead of terminating the write cycle after
the receipt of the first data word. After receiving each data packet the internal address counter is
incremented by one, and the next data is automatically taken into the next address. The address counter
will “roll over” to 00H and the data of 00H will be read out if the address exceeds “4FH” of Register map
prior to generating a stop condition.
The AK4951A supports two basic read operations: CURRENT ADDRESS READ and RANDOM
ADDRESS READ.
2-1. CURRENT ADDRESS READ
The AK4951A has an internal address counter that maintains the address of the last accessed word
incremented by one. Therefore, if the last access (either a read or write) were to address “n”, the next
CURRENT READ operation would access data from the address “n+1”. After receipt of the slave address
with R/W bit “1”, the AK4951A generates an acknowledge, transmits 1-byte of data to the address set by
the internal address counter and increments the internal address counter by 1. If the master does not
generate an acknowledge but generates a stop condition instead, the AK4951A ceases the transmission.
SDA
S
T
R/W ="1"
A
R
T
Slave
S _Address
Data(n)
Data(n+1)
Data(n+2)
A
MA
MA
MA
C
AC
AC
AC
K
SK
SK
SK
T
T
T
E
E
E
R
R
R
Figure 53. Current Address Read
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
SK
SC
T
TK
E
E
R
R
2-2. RANDOM ADDRESS READ
The random read operation allows the master to access any memory location at random. Prior to issuing
the slave address with the R/W bit “1”, the master must first perform a “dummy” write operation. The
master issues a start request, a slave address (R/W bit = “0”) and then the register address to read. After
the register address is acknowledged, the master immediately reissues the start request and the slave
address with the R/W bit “1”. The AK4951A then generates an acknowledge, 1 byte of data and
increments the internal address counter by 1. If the master does not generate an acknowledge but
generates a stop condition instead, the AK4951A ceases the transmission.
S
T
R/W ="0"
A
R
T
S
T
R/W ="1"
A
R
T
SDA
Slave
S _Address
Sub
Address(n)
Slave
S _Address
Data(n)
Data(n+1)
A
A
A
MA
MA
C
C
C
AC
AC
K
K
K
SK
SK
T
T
E
E
R
R
Figure 54. Random Address Read
S
T
O
P
Data(n+x)
P
MA
MN
AC
AA
SK
SC
T
TK
E
E
R
R
016001936-E-00
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2016/03