AK4951AEN Datasheet, PDF (39/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
2. Interface
The input data channel of the DMDAT pin is set by DCLKP bit. When DCLKP bit = “1”, L channel data is
input to the decimation filter if DMCLK = “H”, and R channel data is input if DMCLK = “L”. When DCLKP bit
= “0”, R channel data is input to the decimation filter while DMCLK pin= “H”, and L channel data is input
while DMCLK pin= “L”. The DMCLK pin only supports 64fs. It outputs “L” when DCLKE bit = “0”, and
outputs 64fs when DCLKE bit = “1”. In this case, necessary clocks must be supplied to the AK4951A for
ADC operation. The output data through “the Decimation and Digital Filters” is 24bit full scale when the
1bit data density is 0%~100%.
Table 25. Data In/Output Timing with Digital Microphone (DCLKP bit = “0”)
DCLKP bit DMCLK pin= “H” DMCLK pin= “L”
0
Rch
Lch
(default)
1
Lch
Rch
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 28. Data In/Output Timing with Digital Microphone (DCLKP bit = “1”)
DMCLK(64fs)
DMDAT (Lch)
DMDAT (Rch)
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Valid
Data
Figure 29. Data In/Output Timing with Digital Microphone (DCLKP bit = “0”)
016001936-E-00
- 39 -
2016/03