AK4951AEN Datasheet, PDF (67/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ Serial Control Interface
The AK4951A supports the fast-mode I²C Bus (max: 400kHz). Pull-up resistors at the SDA and SCL pins
must be connected to a voltage in the range from TVDD or more to 6V or less.
1. WRITE Operations
Figure 49 shows the data transfer sequence for the I²C Bus mode. All commands are preceded by a
START condition. A HIGH to LOW transition on the SDA line while SCL is HIGH indicates a START
condition (Figure 55). After the START condition, a slave address is sent. This address is 7 bits long
followed by the eighth bit that is a data direction bit (R/W). The most significant seven bits of the slave
address are fixed as “0010010” (Figure 50). If the slave address matches that of the AK4951A, the
AK4951A generates an acknowledge and the operation is executed. The master must generate the
acknowledge-related clock pulse and release the SDA line (HIGH) during the acknowledge clock pulse
(Figure 56). A R/W bit value of “1” indicates that the read operation is to be executed, and “0” indicates
that the write operation is to be executed.
The second byte consists of the control register address of the AK4951A. The format is MSB first, and
those most significant 1bit is fixed to zero (Figure 51). The data after the second byte contains control
data. The format is MSB first, 8bits (Figure 52). The AK4951A generates an acknowledge after each byte
is received. Data transfer is always terminated by a STOP condition generated by the master. A LOW to
HIGH transition on the SDA line while SCL is HIGH defines a STOP condition (Figure 55).
The AK4951A can perform more than one byte write operation per sequence. After receipt of the third
byte the AK4951A generates an acknowledge and awaits the next data. The master can transmit more
than one byte instead of terminating the write cycle after the first data byte is transferred. After receiving
each data packet the internal address counter is incremented by one, and the next data is automatically
taken into the next address. The address counter will “roll over” to 00H and the previous data will be
overwritten if the address exceeds “4FH” prior to generating a stop condition.
The data on the SDA line must remain stable during the HIGH period of the clock. HIGH or LOW state of
the data line can only be changed when the clock signal on the SCL line is LOW (Figure 57) except for the
START and STOP conditions.
016001936-E-00
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2016/03