AK4951AEN Datasheet, PDF (25/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ PLL Mode
When PMPLL bit is “1”, a fully integrated analog phase locked loop (PLL) circuit generates a clock that is
selected by PLL3-0 and FS3-0 bits. The PLL lock times, when the AK4951A is supplied stable clocks after
PLL is powered-up (PMPLL bit = “0” → “1”) or the sampling frequency is changed, are shown in Table 5.
1) PLL Mode Reference Clock Setting
Table 5. PLL Mode Setting
Mode
PLL3 PLL2 PLL1 PLL0
bit bit bit bit
PLL Reference
Clock Input Pin
Input
Frequency
0
0
0
0
0
MCKI pin
16MHz
2
0
0
1
0
BICK pin
32fs
3
0
0
1
1
BICK pin
64fs
4
0
1
0
0
MCKI pin 11.2896MHz
5
0
1
0
1
MCKI pin
12.288MHz
6
0
1
1
0
MCKI pin
12MHz
7
0
1
1
1
MCKI pin
24MHz
12
1
1
0
0
MCKI pin
13.5MHz
13
1
1
0
1
MCKI pin
27MHz
Others
Others
N/A
(*fs: Sampling Frequency, N/A: Not Available)
PLL Lock Time
(max)
5ms
2ms
2ms
5ms
5ms
5ms
5ms
5ms
5ms
(default)
2) Setting of sampling frequency in PLL Mode (PLL reference clock input pin = MCKI pin)
When PLL reference clock input is MCKI pin, the sampling frequency is selected by FS3-0 bits as defined
in Table 6.
Table 6. Setting of Sampling Frequency (Reference Clock = MCKI pin)
Mode FS3 bit
FS2 bit
FS1 bit
FS0 bit
Sampling Frequency
(Note 32)
0
0
0
0
0
8kHz mode
1
0
0
0
1
12kHz mode
2
0
0
1
0
16kHz mode
5
0
1
0
1
11.025kHz mode
7
0
1
1
1
22.05kHz mode
9
1
0
0
1
24kHz mode
10
1
0
1
0
32kHz mode
11
1
0
1
1
48kHz mode
(default)
15
1
1
1
1
44.1kHz mode
Others
Others
N/A
(N/A: Not Available)
Note 32. When the MCKI pin is the PLL reference clock input, the sampling frequency generated by PLL
differs from the sampling frequency of mode name in some combinations of MCKI
frequency(PLL3-0 bits) and sampling frequency (FS3-0 bits). Refer to Table 7 for the details of
sampling frequency. In master mode, LRCK and BICK output frequency correspond to sampling
frequencies shown in Table 7.
016001936-E-00
- 25 -
2016/03