AK4951AEN Datasheet, PDF (29/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 16MHz, 24MHz or 27MHz) is input
to the MCKI pin, the internal PLL circuit generates BICK and LRCK clocks. When the state of AK4951A is
ADC power-down or Loopback mode, the output of BICK, LRCK and SDTO pins can be stopped by
CKOFF bit. When CKOFF bit = “1”, BICK, LRCK and SDTO pins output “L”. The BICK output frequency is
selected between 32fs or 64fs, by BCKO bit (Table 10).
AK4951A
11.2896MHz, 12MHz, 12.288MHz,
13.5MHz, 16MHz, 24MHz, 27MHz
DSP or P
MCKI
BICK
LRCK
SDTO
SDTI
32fs, 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 15. PLL Master Mode
Table 10. BICK Output Frequency at Master Mode
BCKO bit
BICK Output Frequency
0
32fs
(default)
1
64fs
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the BICK pin. The required clock for the
AK4951A is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
The BICK and LRCK inputs must be synchronized. The sampling frequency can be selected by FS3-0
bits (Table 6).
AK4951A
DSP or P
MCKI
BICK
LRCK
SDTO
SDTI
32fs or 64fs
1fs
BCLK
LRCK
SDTI
SDTO
Figure 16. PLL Slave Mode (PLL Reference Clock: BICK pin)
016001936-E-00
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2016/03