AK4951AEN Datasheet, PDF (65/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
LOUT 1F
ROUT
220
External
Input
22k
Note 43. If the value of 22k resistance at pop noise reduction circuit is increased, the power-up time of
stereo line output is increased but the pop noise level is not decreased. Do not use a resistor less
than 22k at the pop noise reduction circuit since the line output drivability is minimum 10k.
Figure 45. External Circuit for Stereo Line Output (in case of using a Pop Noise Reduction Circuit)
[Stereo Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit)]
LOSEL bit
PMSL bit
(1)
(2)
(3)
SLPSN bit
(6)
(5)
(4)
LOUT, ROUT pins
Normal Output
99%
Common Voltage
1%
Common Voltage
300 ms
300 ms
Figure 46. Stereo Line Output Control Sequence (in case of using a Pop Noise Reduction Circuit)
(1) Set LOSEL bit = “1”. Enable stereo line output.
(2) Set PMSL bit = “1”. Stereo line output exits power-down mode.
LOUT and ROUT pins rise up to common voltage. Rise time to 99% common voltage is 200ms
(max. 300ms) when C=1F.
(3) Set SLPSN bit = “0” after LOUT and ROUT pins rise up. Stereo line output exits power-save
mode.
Stereo line output is enabled.
(4) Set SLPSN bit = “1”. Stereo line output enters power-save mode.
(5) Set PMSL bit = “0”. Stereo line output enters power-down mode.
LOUT and ROUT pins fall down to 1% of the common voltage. Fall time is 200ms (max.
300ms) when C=1F.
(6) Set LOSEL bit = “0” after wait time (≥300ms). Disable stereo line output.
016001936-E-00
- 65 -
2016/03