AK4951AEN Datasheet, PDF (70/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
SDA
SCL
S
start condition
P
stop condition
Figure 55. Start Condition and Stop Condition
DATA
OUTPUT BY
TRANSMITTER
DATA
OUTPUT BY
RECEIVER
SCL FROM
MASTER
S
START
CONDITION
not acknowledge
1
2
acknowledge
8
9
Figure 56. Acknowledge (I²C Bus)
clock pulse for
acknowledgement
SDA
SCL
data line
stable;
data valid
change
of data
allowed
Figure 57. Bit Transfer (I²C Bus)
016001936-E-00
- 70 -
2016/03