AK4951AEN Datasheet, PDF (28/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
■ PLL Unlock State
In this mode, LRCK and BICK pins go to “L” until the PLL goes to lock state after PMPLL bit = “0” → “1”
(Table 9).
After the PLL is locked, a first period of LRCK and BICK may be invalid clock, but these clocks return to
normal state after a period of 1/fs.
The BICK and LRCK pins do not output invalid clocks such as PLL unlock state by setting PMPLL bit to
“0”. During PMPLL bit = “0”, these pins output the same clock as EXT master mode.
Table 9. Clock Operation at PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
PLL State
BICK pin
LRCK pin
After PMPLL bit “0” → “1”
“L” Output
“L” Output
PLL Unlock (except the case above)
Invalid
Invalid
PLL Lock
Table 10
1fs Output
016001936-E-00
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2016/03