AK4951AEN Datasheet, PDF (18/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
Parameter
Symbol Min.
Typ.
External Master Mode
MCKI Input Timing
Frequency
256fs
fCLK
2.048
-
384fs
fCLK
3.072
-
512fs
fCLK
4.096
-
1024fs
fCLK
8.192
-
Pulse Width Low
tCLKL 0.4/fCLK
-
Pulse Width High
tCLKH 0.4/fCLK
-
LRCK Output Timing
Frequency
CM1-0 bits = “00”
fs
-
fCLK/256
CM1-0 bits = “01”
fs
-
fCLK/384
CM1-0 bits = “10”
fs
CM1-0 bits = “11”
fs
-
fCLK/512
-
fCLK/1024
Duty Cycle
Duty
-
50
BICK Output Timing
Frequency
BCKO bit = “0”
fBCK
-
32fs
BCKO bit = “1”
fBCK
-
64fs
Duty Cycle
dBCK
-
50
Audio Interface Timing
Master Mode
BICK “” to LRCK Edge (Note 24)
tBLR
40
-
LRCK Edge to SDTO (MSB)
tLRD
70
-
(Except I²S mode)
BICK “” to SDTO
tBSD
70
-
SDTI Hold Time
tSDH
50
-
SDTI Setup Time
tSDS
50
-
Slave Mode
LRCK Edge to BICK “” (Note 24)
tLRB
50
-
BICK “” to LRCK Edge (Note 24)
tBLR
50
-
LRCK Edge to SDTO (MSB)
tLRD
-
-
(Except I²S mode)
BICK “” to SDTO
SDTI Hold Time
tBSD
-
-
tSDH
50
-
SDTI Setup Time
tSDS
50
-
Digital Audio Interface Timing; C_L=100pF
DMCLK Output Timing
Period
tSCK
-
1/(64fs)
Rising Time
tSRise
-
-
Falling Time
tSFall
-
-
Duty Cycle
dSCK
40
50
Audio Interface Timing
DMDAT Setup Time
tDSDS
50
-
DMDAT Hold Time
tDSDH
0
-
Note 24. BICK rising edge must not occur at the same time as LRCK edge.
Max.
12.288
18.432
24.576
24.576
-
-
-
-
-
-
-
-
-
-
40
70
70
-
-
-
-
80
80
-
-
-
10
10
60
-
-
Unit
MHz
MHz
MHz
MHz
s
s
Hz
Hz
Hz
Hz
%
Hz
Hz
%
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
s
ns
ns
%
ns
ns
016001936-E-00
- 18 -
2016/03