AK4951AEN Datasheet, PDF (62/105 Pages) Asahi Kasei Microsystems – 24bit Stereo CODEC with MIC/HP/SPK-AMP

[AK4951A]
PMVCM PMHPL/R
bit
bits
x
0
x
0
1
1
1
1
(x: Do not care)
Table 55. Headphone Output Status
HPZ bit
Mode
HPL/R pins
0
Power-down & Mute Pull-down by 10 (typ)
1
Power-down
Hi-Z
0
Normal Operation
Normal Operation
1
Normal Operation
Normal Operation
(default)
■ Speaker Output (SPP/SPN pins, LOSEL bit = “0”)
When LOSEL bit = “0”, the DAC output signal is input to the speaker amplifier as mono signal [(L+R)/2].
The speaker amplifier has mono output as it is BTL capable. The gain and output level are set by
SPKG1-0 bits. The output level depends on SVDD and SPKG1-0 bits setting.
Table 56. SPK-Amp Gain
SPKG1-0
bits
Gain
SPK-Amp Output Level
(DAC Input =0dBFS, SVDD=3.3V)
00
+6.4dB
3.37Vpp
(default)
01
+8.4dB
4.23Vpp (Note 41)
10
+11.1dB
5.33Vpp (Note 41)
11
+14.9dB
8.47Vpp
(SVDD=5.0V; Note 41)
Note 41. The output level is calculated on the assumption that the signal is not clipped. However, in the
actual case, the SPK-Amp output signal is clipped when DAC outputs 0dBFS signal. The
SPK-Amp output level should be kept under 4.0Vpp (SVDD=3.3V) by adjusting digital volume to
prevent clipped noise.
< Speaker-Amp Control Sequence >
The speaker amplifier is powered-up/down by PMSL bit. When PMSL bit is “0” at LOSEL bit = “0”, both
SPP and SPN pins are pulled-down to VSS3 by 100kΩ (typ). When PMSL bit is “1” and SLPSN bit is “0”
at LOSEL bit = “0”, the speaker amplifier enters power-save mode. In this mode, the SPP pin is placed in
Hi-Z state and the SPN pin outputs SVDD/2 voltage (Note 42).
When the PMSL bit is “1” at LOSEL bit = “0” after the PDN pin is changed from “L” to “H”, the SPP and
SPN pins rise up in power-save mode. In this mode, the SPP pin is placed in a Hi-Z state and the SPN pin
goes to SVDD/2 voltage (Note 42). Because the SPP and SPN pins rise up in power-save mode, pop
noise can be reduced. When the AK4951A is powered-down (PMSL bit = “0”), pop noise can also be
reduced by first entering power-save-mode.
Note 42. When the SVDD more than 4.6V is supplied, the voltage cannot rise up to SVDD/2.
PMSL SLPSN
bit
bit
0
x
1
0
1
(x: Do not care)
Table 57 Speaker-Amp Mode Setting
Mode
SPP pin
SPN pin
Power-down
Power-save
Normal Operation
Pull-down to VSS3
Hi-Z
Normal Operation
Pull-down to VSS3
SVDD/2 (Note 42)
Normal Operation
(default)
016001936-E-00
- 62 -
2016/03