AK4373 Datasheet, PDF (95/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ Stop of Clock
Master clock can be stopped when DAC is not used.
1. PLL Master Mode
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
"1" or "0"
Input
(1)
(2)
(3)
Example:
Audio I/F Format: MSB justified
BICK frequency at Master Mode: 64fs
Input Master Clock Select at PLL Mode: 11.2896MHz
(1) (2) Addr:01H, Data:08H
(3) Stop an external MCKI
Figure 78. Clock Stopping Sequence (1)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop MCKO clock: MCKO bit = “1” → “0”
(3) Stop an external master clock.
2. PLL Slave Mode (LRCK or BICK pin)
PMPLL bit
(Addr:01H, D0)
External BICK
External LRCK
(1)
(2)
Input
(2)
Input
Example
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 79. Clock Stopping Sequence (2)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
(2) Stop the external BICK and LRCK clocks
3. PLL Slave (MCKI pin)
PMPLL bit
(Addr:01H, D0)
MCKO bit
(Addr:01H, D1)
External MCKI
(1)
(1)
(2)
Input
Example
Audio I/F Format: MSB justified
PLL Reference clock: MCKI
BICK frequency: 64fs
(1) Addr:01H, Data:00H
(2) Stop the external clocks
Figure 80. Clock Stopping Sequence (3)
<Example>
(1) Power down PLL: PMPLL bit = “1” → “0”
Stop MCKO output: MCKO bit = “1” → “0”
(2) Stop the external master clock.
MS0991-E-00
- 95 -
2008/09