AK4373 Datasheet, PDF (55/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
When writing to the AVL7-0 and AVR7-0 bits continuously, the control register should be written by an interval more
than zero crossing timeout. If not, AVL and AVR are not changed since zero crossing counter is reset at every write
operation. If the same register value as the previous write operation is written to AVL and AVR, this write operation is
ignored and zero crossing counter is not reset. Therefore, AVL and AVR can be written by an interval less than zero
crossing timeout.
ALC bit
ALC Status
Disable
Enable
Disable
AVL7-0 bits
E1H(+30dB)
AVR7-0 bits
C6H(+20dB)
Internal AVL
Internal AVR
E1H(+30dB)
C6H(+20dB)
E1(+30dB) --> F1(+36dB)
(1)
E1(+30dB) --> F1(+36dB)
E1(+30dB)
(2)
C6H(+20dB)
Figure 48. AVOL value during ALC operation
(1) The AVL value becomes the start value if the AVL and AVR are different when the ALC starts. The wait time from
ALC bit = “1” to ALC operation start by AVL7-0 bits is at most recovery time (WTM2-0 bits) plus zerocross timeout
period (ZTM1-0 bits).
(2) Writing to AVL and AVR registers (09H and 0CH) is ignored during ALC operation. After ALC is disabled, the
AVOL changes to the last written data by zero crossing or timeout. When ALC is enabled again, ALC bit should be
set to “1” by an interval more than zero crossing timeout period after ALC bit = “0”.
MS0991-E-00
- 55 -
2008/09