AK4373 Datasheet, PDF (60/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ Stereo Line Output (LOUT/ROUT pins)
The common voltage is 0.5 x HVDD when VBAT bit = “0” (Table 40). The load resistance is 10kΩ (min).
Stereo line out amplifier is shared with Headphone amplifier (HPBTL bit = PSEUDO bit = “0” in Table 38). When
PMHPL/R and HPMTN bits are “1”, the stereo line output is powered-up (Figure 52).
Stereo line out amplifier is prohibited from using headphone output at the same time.
■ Headphone Output
The power supply voltage for the Headphone-Amp is supplied from the HVDD pin and the output level is centered on the
HVDD/2 when VBAT bit = “0”. If HVDD voltage becomes lower, the output signal might be distorted while the
amplitude is maintained. The load resistance is 16Ω (min). HPBTL and PSEUDO bits select the output type, Single-ended
or Differential or Pseudo cap-less. When the HPBTL bit is “1”, HPL/HPR/SPP/SPN pins become
HPL+/HPL-/HPR+/HPR- pins, respectively. When the PSEUDO bit is “1”, the SPN pin become the HVCM pin. HPG bit
selects the output voltage (Table 38).
HPBTL PSEUDO HPG
Output Type
Output pins
Output Voltage [Vpp]
0
0
0
Single-ended
HPL, HPR
0.6 x AVDD
0
0
1
Single-ended
HPL, HPR
0.91 x AVDD
1
0
0
Differential
HPL+/-, HPR+/-
1.2 x AVDD
1
0
1
Differential
HPL+/-, HPR+/-
1.82 x AVDD
0
1
0
Pseudo cap-less
HPL, HPR, HVCM
0.6 x AVDD
0
1
1
Pseudo cap-less
HPL, HPR, HVCM
0.91 x AVDD
1
1
x
N/A
Table 38. Headphone-Amp Output Type and Output Voltage (x: Don’t care, N/A: Not available)
When the HPMTN bit is “0”, the common voltage of Headphone-Amp falls and the outputs (HPL/R and HPL+/- and
HPR+/- and HVCM pins) go to “L” (VSS2). When the HPMTN bit is “1”, the common voltage rises to HVDD/2 at
VBAT bit = “0”. A capacitor between the MUTET pin and ground reduces pop noise at power-up. Rise/Fall time constant
is in proportional to HVDD voltage and the capacitor at MUTET pin.
[Example]: A capacitor between the MUTET pin and ground = 1.0μF±30%, HVDD=3.6V:
Rising time (0.8 x HVDD/2): 150ms(typ), 260ms(max) at HPMTN bit = “0” Æ “1”
Time until the common voltage goes to VSS2: 140ms(typ), 260ms(max) at HPMTN bit = “1” Æ “0”
When PMHPL and PMHPR bits are “0”, the Headphone-Amp is powered-down, and the outputs (HPL and HPR pins) go
to “L” (VSS2).
PMHPL bit,
PMHPR bit
HPMTN bit
HPL/R pins
HPL+/- pins
HPR+/- pins
HVCM pin
(1) (2)
(3)
(4)
Figure 52. Power-up/Power-down Timing for Headphone-Amp
(1) Headphone-Amp power-up (PMHPL, PMHPR bit = “1”). The outputs are still VSS2.
(2) Headphone-Amp common voltage rises up (HPMTN bit = “1”). Common voltage of Headphone-Amp is rising.
(3) Headphone-Amp common voltage falls down (HPMTN bit = “0”). Common voltage of Headphone-Amp is falling.
(4) Headphone-Amp power-down (PMHPL, PMHPR bit = “0”). The outputs are VSS2. If the power supply is switched
off or Headphone-Amp is powered-down before the common voltage changes to VSS2, POP noise occurs.
MS0991-E-00
- 60 -
2008/09