AK4373 Datasheet, PDF (33/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ PLL Slave Mode (PMPLL bit = “1”, M/S bit = “0”)
A reference clock of PLL is selected among the input clocks to the MCKI, BICK or LRCK pin. The required clock to the
AK4373 is generated by an internal PLL circuit. Input frequency is selected by PLL3-0 bits (Table 5).
a) PLL reference clock: MCKI pin
BICK and LRCK inputs must be synchronized with MCKO output. The phase between MCKO and LRCK is not
important. The MCKO pin outputs the frequency selected by PS1-0 bits (Table 10) and the output is enabled by MCKO
bit. Sampling frequency can be selected by FS3-0 bits (Table 6).
AK4373
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 25MHz, 27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
256fs/128fs/64fs/32fs
≥ 32fs
1fs
MCLK
BCLK
LRCK
SDTI
SDTO
Figure 25. PLL Slave Mode 1 (PLL Reference Clock: MCKI pin)
MS0991-E-00
- 33 -
2008/09