AK4373 Datasheet, PDF (35/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”)
When PMPLL bit is “0”, the AK4373 changes to EXT mode. Master clock is input from the MCKI pin, the internal PLL
circuit is not operated. This mode is compatible with I/F of a normal audio DAC. The clocks required to operate are MCKI
(256fs, 512fs or 1024fs), LRCK (fs) and BICK (≥32fs). The master clock (MCKI) should be synchronized with LRCK.
The phase between these clocks is not important. The input frequency of MCKI is selected by FS1-0 bits (Table 12).
Mode
0
1
2
3
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
x
0
1
1024fs
7.35kHz ∼ 13kHz
x
1
0
512fs
7.35kHz ∼ 26kHz
x
1
1
512fs
7.35kHz ∼ 48kHz
Table 12. MCKI Frequency at EXT Slave Mode (PMPLL bit = “0”, M/S bit = “0”) (x: Don’t care)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through HPL/HPR pins at fs=8kHz is shown in Table 13.
Mode
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
0
256fs
2
512fs
56dB
3
512fs
75dB
1
1024fs
93dB
Table 13. Relationship between MCKI and S/N of HPL/HPR pins
The external clocks (MCKI, BICK and LRCK) should always be present whenever the DAC is in operation (PMDAC bit
= “1”). If these clocks are not provided, the AK4373 may draw excess current and it is not possible to operate properly
because utilizes dynamic refreshed logic internally. If the external clocks are not present, the DAC must be in the
power-down mode (PMDAC bit = “0”).
AK4373
MCKO
MCKI
BICK
LRCK
SDTI
256fs, 512fs or 1024fs
DSP or μP
MCLK
≥ 32fs
BCLK
1fs
LRCK
SDTO
Figure 28. EXT Slave Mode
MS0991-E-00
- 35 -
2008/09