AK4373 Datasheet, PDF (64/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ Speaker Output (SPP/SPN pins)
Recommended power supply range is 2.6V to 4.0V. If HVDD voltage becomes low, the output signal might be distorted
while the amplitude is maintained. Speaker-Amp is available at HPBTL bit = PSEUDO bit = “0”.
Speaker Type
Dynamic Speaker
Piezo (Ceramic) Speaker
Load Resistance (min)
8Ω
50Ω
Load Capacitance (max)
30pF
3μF
Note 21. Load impedance is total impedance of series resistance (Rseries) and piezo speaker impedance at 1kHz in
34HFigure 56. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 20Ω or more series
resistors should be connected at both SPP and SPN pins, respectively.
Table 41. Speaker Type and Power Supply Range
The DAC signal is input to the Speaker-amp as [(L+R)/2]. The Speaker-amp is mono and BTL output. The gain is set by
SPKG1-0 bits. Output level depends on AVDD voltage and SPKG1-0 bits.
SPKG1-0 bits
00
01
10
11
Gain
ALC bit = “0”
ALC bit = “1”
+4.43dB
+6.43dB
+6.43dB
+8.43dB
+10.65dB
+12.65dB
+12.65dB
+14.65dB
Table 42. SPK-Amp Gain
(default)
SPK-Amp Output (DAC Input = 0dBFS)
AVDD HVDD SPKG1-0 bits
ALC bit = “0”
ALC bit = “1”
(LMTH1-0 bits = “00”)
00
3.30Vpp
3.11Vpp
3.3V
01
4.15Vpp (Note 45)
3.92Vpp
10
6.75Vpp (Note 45)
6.37Vpp (Note 45)
3.3V
11
8.50Vpp (Note 45)
8.02Vpp (Note 45)
00
3.30Vpp
3.11Vpp
4.0V
01
4.15Vpp
3.92Vpp
10
6.75Vpp (Note 45)
6.37Vpp (Note 45)
11
8.50Vpp (Note 45)
8.02Vpp (Note 45)
Note 45. The output level is calculated by assuming that output signal is not clipped. In actual case, output signal may be
clipped when DAC outputs 0dBFS signal. DAC output level should be set to lower level by setting digital
volume so that Speaker-Amp output level is 4.0Vpp (HVDD=3.3V) or 4.8Vpp (HVDD=4V) or less and output
signal is not clipped.
Table 43. SPK-Amp Output Level
MS0991-E-00
- 64 -
2008/09