AK4373 Datasheet, PDF (50/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ ALC Operation
The ALC (Automatic Level Control) is controlled by ALC block when ALC bit is “1”.
1. ALC Limiter Operation
During ALC limiter operation, when either Lch or Rch exceeds the ALC limiter detection level (Table 22), the AVL and
AVR values (same value) are attenuated automatically by the amount defined by the ALC limiter ATT step (Table 23).
When ZELMN bit = “0” (zero cross detection is enabled), the AVL and AVR values are changed by ALC limiter
operation at the individual zero crossing points of Lch and Rch or at the zero crossing timeout. ZTM1-0 bits set the zero
crossing timeout period of both ALC limiter and recovery operation (Table 24). When ALC output level exceeds
full-scale, IVL and IVR values are immediately (Period: 1/fs) changed. When ALC output level is less than full-scale,
IVL and IVR values are changed at the individual zero crossing point of each channels or at the zero crossing timeout.
When ZELMN bit = “1” (zero cross detection is disabled), AVL and AVR values are immediately (period: 1/fs) changed
by ALC limiter operation. Attenuation step is fixed to 1 step regardless of the setting of LMAT1-0 bits.
The attenuate operation is done continuously until the input signal level becomes ALC limiter detection level (Table 22)
or less. After completing the attenuate operation, unless ALC bit is changed to “0”, the operation repeats when the input
signal level exceeds LMTH1-0 bits.
LMTH1
0
0
1
1
LMTH0 ALC Limier Detection Level ALC Recovery Waiting Counter Reset Level
0
ALC Output ≥ −2.5dBFS
−2.5dBFS > ALC Output ≥ −4.1dBFS
1
ALC Output ≥ −4.1dBFS
−4.1dBFS > ALC Output ≥ −6.0dBFS
0
ALC Output ≥ −6.0dBFS
−6.0dBFS > ALC Output ≥ −8.5dBFS
1
ALC Output ≥ −8.5dBFS
−8.5dBFS > ALC Output ≥ −12dBFS
Table 22. ALC Limiter Detection Level / Recovery Counter Reset Level
(default)
LMAT1
0
0
1
1
LMAT0
ALC1 Limiter ATT Step (0.375dB/step)
ALC1 Output ≥ LMTH
0
1
1
2
0
2
1
1
Table 23. ALC Limiter ATT Step
(default)
ZTM1
0
0
1
1
ZTM0
0
1
0
1
Zero Crossing Timeout Period
8kHz
16kHz
44.1kHz
128/fs
16ms
8ms
2.9ms
256/fs
32ms
16ms
5.8ms
512/fs
64ms
32ms
11.6ms
1024/fs
128ms
64ms
23.2ms
Table 24. ALC Zero Crossing Timeout Period
(default)
MS0991-E-00
- 50 -
2008/09