AK4373 Datasheet, PDF (37/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ System Reset
The PDN pin must be held to “L” upon power-up. The 4373 should be reset by bringing PDN pin “L” for 150ns or more.
All of the internal register values are initialized by the system reset. After exiting reset, VCOM, DAC, HPL, HPR, LOUT,
ROUT, SPP and SPN switch to the power-down state. The contents of the control register are maintained until the reset is
completed.
The DAC exits reset and power down states by MCKI after the PMDAC bit is changed to “1”. The DAC is in power-down
mode until MCKI is input.
■ Audio Interface Format
Three types of data formats are available and are selected by setting the DIF1-0 bits (Table 17). In all modes, the serial
data is MSB first, 2’s complement format. Audio interface formats can be used in both master and slave modes. LRCK
and BICK are output from the AK4373 in master mode, but must be input to the AK4373 in slave mode.
Mode
0
1
2
3
4
5
6
7
DIF2 bit
0
0
0
0
1
1
1
1
DIF1 bit
0
0
1
1
0
0
1
1
DIF0 bit
0
1
0
1
0
1
0
1
SDTI (DAC)
BICK
16 bit DSP Mode
≥32fs
16 bit LSB justified
≥32fs
16/20/24 bit MSB justified
16/20/24 bit I²S compatible
32fs or ≥48fs
32fs or ≥48fs
20 bit LSB justified
≥40fs
24 bit LSB justified
≥48fs
20 bit DSP Mode
≥40fs
24 bit DSP Mode
≥48fs
Table 17. Audio Interface Format
Figure
Table 18
Figure 34
Figure 36
Figure 37
Figure 35
Figure 35
Table 18
Table 18
(default)
In Modes 1- 5 the SDTI is latched on the rising edge (“↑”) of BICK.
In Modes 0/6/7 (DSP mode), the audio I/F timing is changed by BCKP and MSBS bits (Table 18, Table 19 and Table 20).
DIF2
0
DIF1
0
DIF0
0
MSBS
0
0
1
1
BCKP
Audio Interface Format
MSB of SDTI is latched by the falling edge (“↓”) of the BICK
0 just after the rising edge (“↑”) of the first BICK after the rising
edge (“↑”) of LRCK.
MSB of SDTI is latched by the rising edge (“↑”) of the BICK
1 just after the falling edge (“↓”) of the first BICK after the rising
edge (“↑”) of LRCK.
0
MSB of SDTI is latched by the 2nd falling edge (“↓”) of the
BICK after the rising edge (“↑”) of LRCK.
1
MSB of SDTI is latched by the 2nd rising edge (“↑”) of the
BICK after the rising edge (“↑”) of LRCK..
Table 18. Audio Interface Format in Mode 0
Figure
Figure 30
Figure 31
Figure 32
Figure 33
(default)
MS0991-E-00
- 37 -
2008/09