AK4373 Datasheet, PDF (94/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ Headphone-amp Output (Single-Ended or Differential or Pseudo cap-less)
FS3-0 bits _0,000
(Addr:05H, D5&D2-0)
DACH bit
(Addr:0FH, D0)
(1)
(2)
1,111
HPBTL,PSEU
DO bits
(Addr:02H, D3,D1)
IVL/R7-0 bits
(Addr:09H&0CH, D7-0)
DVL/R7-0 bits
(Addr:0AH&0DH, D7-0)
PMDAC bit
(Addr:00H, D2)
PMMIN bit
(Addr:00H, D5)
"0"
E1H
"00"(Single-ended)/ "10"(Full-
Differential)/ "01"(Pseudo cap-less)
(3)
91H
(4)
18H
(5)
28H
(6)
(11)
(12)
Example:
PLL, Master M ode
Audio I/F F ormat :MSB justified
Sam pling Frequency: 44.1kHz
Digital Volume: −8 dB
Bass B oost Level : M iddle
(1) Addr:05H, Data:27H
(2) Addr:0FH, Data:09H
(3) Addr:02H, Data:00H/08H/02H
(4) Addr:09H&0CH, Data:91H
(5) Addr:0AH&0DH, Data:28H
(6) Addr:00H, Data:64H
(7) Addr:01H, Data:39H
PMHPL/R bits
(Addr:01H, D5-4)
HPMTN bit
(Addr:01H, D6)
HPL/R pins
HPL+/- pins
HPR+/- pins
HVCM pin
(7)
(10)
(8)
(9)
Normal Output
(8) Addr:01H, Data:79H
Playback
(9) Addr:01H, Data:39H
(10) Addr:01H, Data:09H
(11) Addr:00H, Data:40H
(12) Addr:0FH, Data:08H
Figure 77. Headphone-Amp Output Sequence
<Example>
At first, clocks should be supplied according to “Clock Set Up” sequence.
(1) Set up a sampling frequency (FS3-0 bits). When the AK4373 is PLL mode, DAC and Speaker-Amp should be
powered-up in consideration of PLL lock time after a sampling frequency is changed.
(2) Set up the path of “DAC → HP-Amp”: DACH bit = “0” → “1”
(3) Select output type of the headphone (HPBTL and PSEUDO bits “00”= Single-ended, “10”=Differential,
“01”=Pseudo cap-less)
(4) Set up the ALC Block Digital Volume (Addr: 09H and 0CH)
AVL7-0 and AVR7-0 bits should be set to “91H”(0dB).
(5) Set up the output digital volume (Addr: 0AH and 0DH)
When DVOLC bit is “1” (default), DVL7-0 bits set the volume of both channels. After DAC is powered-up,
the digital volume changes from default value (0dB) to the register setting value by the soft transition.
(6) Power up DAC: PMDAC bit = “0” → “1”
When ALC bit is “1”, ALC operation starts from the gain set by AVL/R7-0 bits.
(7) Power up headphone-amp: PMHPL = PMHPR bits = “0” → “1”
Output voltage of headphone-amp is still VSS2.
(8) Rise up the common voltage of headphone-amp: HPMTN bit = “0” → “1”
The rise time depends on HVDD and the capacitor value which connected with the MUTET pin. When
HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τr = 100ms(typ), 250ms(max).
(9) Fall down the common voltage of headphone-amp: HPMTN bit = “1” → “0”
The fall time depends on HVDD and the capacitor value which connected with the MUTET pin. When
HVDD=3.3V and the capacitor value is 1.0μF, the time constant is τ f = 100ms(typ), 250ms(max).
If the power supply is powered-off or headphone-Amp is powered-down before the common voltage changes
to GND, the pop noise occurs. It takes twice of τf that the common voltage changes to GND.
(10) Power down headphone-amp: PMHPL = PMHPR bits = “1” → “0”
(11) Power down DAC: PMDAC bit = “1” → “0”
(12) Disable the path of “DAC → HP-Amp”: DACH bit = “1” → “0”
MS0991-E-00
- 94 -
2008/09