AK4373 Datasheet, PDF (32/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ PLL Master Mode (PMPLL bit = “1”, M/S bit = “1”)
When an external clock (11.2896MHz, 12MHz, 12.288MHz, 13.5MHz, 24MHz, 25MHz or 27MHz) is input to the
MCKI pin, the MCKO, BICK and LRCK clocks are generated by an internal PLL circuit. The MCKO output frequency is
selected by PS1-0 bits (Table 10) and the output is enabled by MCKO bit. The BICK output frequency is selected between
32fs or 64fs, by BCKO bit (Table 11).
AK4373
11.2896MHz, 12MHz, 12.288MHz
13.5MHz, 24MHz, 25MHz, 27MHz
DSP or μP
MCKI
MCKO
BICK
LRCK
SDTI
256fs/128fs/64fs/32fs
32fs, 64fs
1fs
MCLK
BCLK
LRCK
SDTO
Figure 24. PLL Master Mode
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 10. MCKO Output Frequency (PLL Mode, MCKO bit = “1”)
BCKO bit
BICK Output
Frequency
0
32fs
(default)
1
64fs
Table 11. BICK Output Frequency at Master Mode
MS0991-E-00
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2008/09