AK4373 Datasheet, PDF (15/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
Mono Input: MIN+/MIN- pins (External Input Resistance=20kΩ) Differential Input
Maximum Input Voltage (Note 24)
-
1.98
Gain (Note 23)
MIN+/- Æ HPL/HPR
HPBTL bit = “0”
HPG bit = “0”
-
0
MIN+/- Æ HPL/HPR
HPBTL bit = “0”
HPG bit = “1”
-
+3.6
MIN+/- Æ HPL+/-, HPR+/-
HPBTL bit = “1”
HPG bit = “0”
-
+6
MIN+/- Æ HPL+/-, HPR+/-
HPBTL bit = “1”
HPG bit = “1”
-
+9.6
MIN+/MIN- Æ SPP/SPN
ALC bit = “0”, SPKG1-0 bits = “00”
-0.07
+4.43
ALC bit = “0”, SPKG1-0 bits = “01”
-
+6.43
ALC bit = “0”, SPKG1-0 bits = “10”
-
+10.65
ALC bit = “0”, SPKG1-0 bits = “11”
-
+12.65
ALC bit = “1”, SPKG1-0 bits = “00”
-
+6.43
ALC bit = “1”, SPKG1-0 bits = “01”
-
+8.43
ALC bit = “1”, SPKG1-0 bits = “10”
-
+12.65
ALC bit = “1”, SPKG1-0 bits = “11”
-
+14.65
-
Vpp
-
dB
-
dB
-
dB
-
dB
+8.93
dB
-
dB
-
dB
-
dB
-
dB
-
dB
-
dB
-
dB
Note 19. Output voltage is proportional to AVDD voltage.
Vout = 1.00 x AVDD(typ)@SPKG1-0 bits = “00”, 1.25 x AVDD(typ)@SPKG1-0 bits = “01”, 2.04 x
AVDD(typ)@SPKG1-0 bits = “10”, 2.57 x AVDD(typ)@SPKG1-0 bits = “11” at Differential output.
Note 20. In case of measuring at SPP and SPN pins.
Note 21. Load impedance is total impedance of series resistance (R_series) and piezo speaker impedance at 1kHz in Figure
56. Load capacitance is capacitance of piezo speaker. When piezo speaker is used, 20Ω or more series resistors
should be connected at both SPP and SPN pins, respectively.
Note 22. Maximum voltage is in proportion to both AVDD and external input resistance (Rin).
Vin = 0.6 x AVDD x 20kΩ (typ)/Rin.
Note 23. The gain is in inverse proportional to external resistance.
Note 24. The Maximum voltage is in proportion to both AVDD and external input resistance (Rin).
Vin = (MIN+) – (MIN-) = 0.6 x AVDD x 20kΩ (typ)/Rin.
The signals with same amplitude and inverted phase should be input to MIN+ and MIN- pins, respectively.
MS0991-E-00
- 15 -
2008/09