AK4373 Datasheet, PDF (63/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
3) Pseudo cap-less Output (HPBTL bit = “0”, PSEUDO bit =”1”)
In case of pseudo cap less, no external AC coupling capacitor is required as well as BTL mode. This pseudo cap less mode
is also available for normal 3-pin headphone mini jack while BTL mode requires a closed system with 4-wire connection.
Power management (power up/down control) of VCOM Amp for HP-Amp is controlled by setting PMHPL bit or
PMHPR bit. The common voltage control of Headphone-Amp and VCOM-Amp is controlled by setting HTMTN bit. The
common voltage is shown in Table 40. PSEUDO bit should be changed when both speaker and headphone amps are
powered-down.
In this mode, HPBTL and DACS and MINS bits must be “0”.
HP-Amp
HPL pin
VCOM Amp for
HP-Amp
HVCM pin
Headphone
R
16Ω
HP-Amp
16Ω
HPR pin
R
Figure 55. External Circuit Example of Headphone (pseudo cap-less output)
<Headphone-Amp PSRR>
When HVDD is directly supplied from the battery in the mobile phone system, RF noise may influences headphone
output performance. When VBAT bit is set to “1”, HP-Amp PSRR for the noise applied to HVDD is improved. In this
case, HP-Amp common voltage is 0.64 x AVDD (typ). When AVDD is 3.3V, common voltage is 2.1V. Therefore, when
HVDD voltage becomes lower than 4.2V, the output signal will be clipped easily.
VBAT bit
0
Common Voltage [V]
0.5 x HVDD
Table 40. HP-Amp Common Voltage
1
0.64 x AVDD
MS0991-E-00
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2008/09