AK4373 Datasheet, PDF (36/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
■ EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”)
The AK4373 becomes EXT Master Mode by setting PMPLL bit = “0” and M/S bit = “1”. Master clock is input from the
MCKI pin, the internal PLL circuit is not operated. The clock required to operate is MCKI (256fs, 512fs or 1024fs). The
input frequency of MCKI is selected by FS1-0 bits (Table 14).
Mode
FS3-2 bits
FS1 bit FS0 bit
MCKI Input
Frequency
Sampling Frequency
Range
0
x
0
0
256fs
7.35kHz ∼ 48kHz (default)
1
x
0
1
1024fs
7.35kHz ∼ 13kHz
2
x
1
0
512fs
7.35kHz ∼ 26kHz
3
x
1
1
512fs
7.35kHz ∼ 48kHz
Table 14. MCKI Frequency at EXT Master Mode (PMPLL bit = “0”, M/S bit = “1”) (x: Don’t care)
The S/N of the DAC at low sampling frequencies is worse than at high sampling frequencies due to out-of-band noise.
The out-of-band noise can be improved by using higher frequency of the master clock. The S/N of the DAC output
through the HPL/HPR pins at fs=8kHz is shown in Table 15.
Mode
MCKI
S/N
(fs=8kHz, 20kHzLPF + A-weighted)
0
256fs
2
512fs
56dB
3
512fs
75dB
1
1024fs
93dB
Table 15. Relationship between MCKI and S/N of HPL/HPR pins
MCKI should always be present whenever the DAC is in operation (PMDAC bit = “1”). If MCKI is not provided, the
AK4373 may draw excess current and it is not possible to operate properly because utilizes dynamic refreshed logic
internally. If MCKI is not present, the DAC should be in the power-down mode (PMDAC bit = “0”).
AK4373
MCKO
MCKI
BICK
LRCK
SDTI
256fs, 512fs or 1024fs
DSP or μP
MCLK
32fs or 64fs
BCLK
1fs
LRCK
SDTO
Figure 29. EXT Master Mode
■ MCKO output frequency
MCKO output frequency can be controlled by PS1/0 bits when MCKO bit is “1” regardless of any clock mode
(PLL/EXT, Master/Slave).
Mode
PS1 bit
PS0 bit
MCKO pin
0
0
0
256fs
(default)
1
0
1
128fs
2
1
0
64fs
3
1
1
32fs
Table 16. MCKO Output Frequency (EXT Mode, MCKO bit = “1”)
MS0991-E-00
- 36 -
2008/09