AK4373 Datasheet, PDF (84/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
SYSTEM DESIGN
Figure 68, Figure 69 and Figure 70 shows the system connection diagram for the AK4373. The evaluation board
[AKD4373] demonstrates the optimum layout, power supply arrangements and measurement results.
[Headphone: Single-ended Mode]
Headphone
Speaker
Power Supply ^10u
2 .2 ∼ 3.6V
ZD2
ZD1
Dyn amic SPK
R1 , R2 : Sho rt
ZD1, ZD 2: Ope n
Pie zo SPK
R1 , R2 : ≥1 0Ω
ZD1, ZD 2: R equ ired
Line Out
Mono In
1u
25 MUTET
0.1u
VSS3 16
1u _{26 ROUT}
DVDD 15
1u _{27 LOUT}
BICK 14
Ri _{28 MIN+}
AK4373EN
LRCK 13
DS P
Ri _{29 MIN-}
Top View
NC 12
30 NC
SDTI 11
31 NC
CDTI 10
32 NC
CCLK 9
μP
Cp
Analog Ground Digital Ground
Notes:
- VSS1, VSS2 and VSS3 of the AK4373 must be distributed separately from the ground of external controllers.
- All digital input pins should not be left floating.
- When the AK4373 is EXT mode (PMPLL bit = “0”), a resistor and a capacitor of the VCOC pin are not needed.
- When the AK4373 is PLL mode (PMPLL bit = “1”), a resistor and a capacitor of the VCOC pin are shown in
Table 5.
- When piezo speaker is used, 2.6 ∼ 4.0V power must be supplied to HVDD and 20Ω or more series resistors
must be connected to both SPP and SPN pins, respectively.
- When the AK4373 is used at master mode, LRCK and BICK pins are floating before M/S bit is changed to “1”.
Therefore, 100kΩ around pull-up resistor must be connected to LRCK and BICK pins of the AK4373.
- If the Analog Mixing block is used as a single-ended, the MIN- pin must be connected to VSS1 in series with a
capacitor to avoid induced external noise.
Figure 68. Typical Connection Diagram (Single-ended mode, HPBTL bit = PSEUDO bit = “0”)
MS0991-E-00
- 84 -
2008/09