AK4373 Datasheet, PDF (21/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

Parameter
Symbol
min
typ
Control Interface Timing (3-wire Serial mode)
CCLK Period
tCCK
200
-
CCLK Pulse Width Low
tCCKL
80
-
Pulse Width High
tCCKH
80
-
CDTI Setup Time
tCDS
40
-
CDTI Hold Time
tCDH
40
-
CSN “H” Time
tCSW
150
-
CSN Edge to CCLK “↑” (Note 37)
tCSS
50
-
CCLK “↑” to CSN Edge (Note 37)
tCSH
50
-
Control Interface Timing (I²C Bus mode): (Note 36)
SCL Clock Frequency
fSCL
-
-
Bus Free Time Between Transmissions
tBUF
1.3
-
Start Condition Hold Time (prior to first clock pulse) tHD:STA
0.6
-
Clock Low Time
tLOW
1.3
-
Clock High Time
tHIGH
0.6
-
Setup Time for Repeated Start Condition
tSU:STA
0.6
-
SDA Hold Time from SCL Falling (Note 38)
tHD:DAT
0
-
SDA Setup Time from SCL Rising
tSU:DAT
0.1
-
Rise Time of Both SDA and SCL Lines
tR
-
-
Fall Time of Both SDA and SCL Lines
tF
-
-
Capacitive Load on Bus
Cb
-
-
Setup Time for Stop Condition
tSU:STO
0.6
-
Pulse Width of Spike Noise Suppressed by Input Filter tSP
0
-
Power-down & Reset Timing
PDN Pulse Width (Note 39)
tPD
150
-
Note 36. I²C is a registered trademark of Philips Semiconductors.
Note 37. CCLK rising edge must not occur at the same time as CSN edge.
Note 38. Data must be held long enough to bridge the 300ns-transition time of SCL.
Note 39. The AK4373 can be reset by the PDN pin = “L”.
[AK4373]
max Units
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
-
ns
400
kHz
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
-
μs
0.3
μs
0.3
μs
400
pF
-
μs
50
ns
-
ns
■ Timing Diagram
1/fCLK
MCKI Input
1000pF
Measurement
Point
100kΩ
VSS3
VSS3
tACW tACW
VAC
Figure 8. MCKI AC Coupling Timing
MS0991-E-00
- 21 -
2008/09