AK4373 Datasheet, PDF (18/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
SWITCHING CHARACTERISTICS
(Ta=-30 ~ 85°C; AVDD=2.2 ∼ 3.6V, DVDD=1.6 ∼ 3.6V; HVDD=2.2 ∼ 4.0V;C_L=20pF; unless otherwise specified)
Parameter
Symbol
min
typ
max
Units
PLL Master Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
AC Pulse Width
tACW
18.5
-
-
ns
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288 MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
%
LRCK Output Timing
Frequency
fs
7.35
-
48
kHz
DSP Mode: Pulse Width High
tLRCKH
-
tBCK
-
ns
Except DSP Mode: Duty Cycle
Duty
-
50
-
%
BICK Output Timing
Period
BCKO bit = “0”
tBCK
-
1/(32fs)
-
ns
BCKO bit = “1”
tBCK
-
1/(64fs)
-
ns
Duty Cycle
dBCK
-
50
-
%
PLL Slave Mode (PLL Reference Clock = MCKI pin)
MCKI Input Timing
Frequency
fCLK
11.2896
-
27
MHz
Pulse Width Low
tCLKL 0.4/fCLK
-
-
ns
Pulse Width High
tCLKH 0.4/fCLK
-
-
ns
MCKO Output Timing
Frequency
fMCK
0.2352
-
12.288 MHz
Duty Cycle
Except 256fs at fs=32kHz, 29.4kHz
dMCK
40
50
60
%
256fs at fs=32kHz, 29.4kHz
dMCK
-
33
-
%
LRCK Input Timing
Frequency
DSP Mode: Pulse Width High
fs
7.35
tLRCKH tBCK−60
-
48
kHz
-
1/fs − tBCK ns
Except DSP Mode: Duty Cycle
Duty
45
-
55
%
BICK Input Timing
Period
tBCK
1/(64fs)
-
1/(32fs)
ns
Pulse Width Low
tBCKL 0.4 x tBCK
-
-
ns
Pulse Width High
tBCKH 0.4 x tBCK
-
-
ns
MS0991-E-00
- 18 -
2008/09