AK4373 Datasheet, PDF (53/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
3. Example of ALC Operation
Table 29 shows the examples of the ALC setting.
Register Name
LMTH1-0
ZELMN
ZTM1-0
WTM2-0
REF7-0
AVL7-0,
AVR7-0
LMAT1-0
RGAIN1-0
RFST1-0
ALC
Comment
fs=8kHz
Data
Operation
Limiter detection Level
01
−4.1dBFS
Limiter zero crossing detection
0
Enable
Zero crossing timeout period
01
32ms
Recovery waiting period
*WTM2-0 bits should be the same or 001
32ms
longer data as ZTM1-0 bits.
Maximum gain at recovery operation E1H
+30dB
Gain of AVOL
E1H
+30dB
Limiter ATT step
00
1 step
Recovery GAIN step
00
1 step
Fast Recovery Speed
00
4 times
ALC enable
1
Enable
Table 29. Example of the ALC setting
fs=44.1kHz
Data
Operation
01
−4.1dBFS
0
Enable
11
23.2ms
011
23.2ms
E1H
+30dB
E1H
+30dB
00
1 step
00
1 step
00
4 times
1
Enable
The following registers should not be changed during ALC operation. These bits should be changed after ALC operation
is finished by ALC bit = “0” or PMDAC bit = “0”.
• LMTH1-0, LMAT1-0, WTM2-0, ZTM1-0, RGAIN1-0, REF7-0, ZELMN, RFST1-0
Manual Mode
Example:
Limiter = Zero crossing Enable
Recovery Cycle = 32ms@8kHz
Limiter and Recovery Step = 1
Maximum Gain = +30.0dB
Limiter Detection Level = −4.1dBFS
ALC bit = “1”
WR (ZTM1-0, WTM2-0, RFST1-0)
(1) Addr=06H, Data=14H
WR (REF7-0)
(2) Addr=08H, Data=E1H
WR (AVL/R7-0) ^{* The value of AVOL should be}
the same or smaller than REF’s
WR (RGAIN1, LMTH1)
(3) Addr=09H&0CH, Data=E1H
(4) Addr=0BH, Data=00H
WR (LMAT1-0, RGAIN0, ZELMN, LMTH0; ALC= “1”)
(5) Addr=07H, Data=01H
ALC Operation
Note : WR : Write
Figure 47. Registers set-up sequence at ALC operation
MS0991-E-00
- 53 -
2008/09