AK4373 Datasheet, PDF (89/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
2. PLL Slave Mode (LRCK or BICK pin)
Power Supply
PDN pin
PMVCM bit
(Addr:00H, D6)
PMPLL bit
(Addr:01H, D0)
LRCK pin
BICK pin
Internal Clock
(1)
(2) (3)
Example:
Audio I/F Format : MSB justified
PLL Reference clock: BICK
BICK frequency: 64fs
Sampling Frequency: 44.1kHz
4f₍s₁o₎ f_{Power Supply & PDN pin = “L” Æ “H”}
(2) Addr:04H, Data:32H
Addr:05H, Data:27H
Input
(4)
(3) Addr:00H, Data:40H
(5)
Figure 72. Clock Set Up Sequence (2)
(4) Addr:01H, Data:01H
<Example>
(2)After Power Up: PDN pin “L” Æ “H”
“L” time of 150ns or more is needed to reset the AK4373.
(3)DIF1-0, FS3-0 and PLL3-0 bits should be set during this period.
(4)Power Up VCOM: PMVCM bit = “0” Æ “1”
VCOM must first be powered up before the other block operates.
(5)PLL starts after the PMPLL bit changes from “0” to “1” and PLL reference clock (LRCK or BICK pin) is
supplied. PLL lock time is 160ms(max) when LRCK is a PLL reference clock. And PLL lock time is 4ms(max)
when BICK is a PLL reference clock.
(6)Normal operation stats after that the PLL is locked.
MS0991-E-00
- 89 -
2008/09