AK4373 Datasheet, PDF (29/98 Pages) Asahi Kasei Microsystems – Low Power Stereo DAC with HP/SPK-Amp

[AK4373]
OPERATION OVERVIEW
■ System Clock
There are the following five clock modes to interface with external devices (Table 2 and Table 3).
Mode
PMPLL bit
M/S bit
PLL3-0 bits
Figure
PLL Master Mode (Note 40)
1
1
See Table 5
Figure 24
PLL Slave Mode 1
(PLL Reference Clock: MCKI pin)
1
0
See Table 5
Figure 25
PLL Slave Mode 2
(PLL Reference Clock: LRCK or BICK pin)
1
0
See Table 5
Figure 26
Figure 27
EXT Slave Mode
0
0
x
Figure 28
EXT Master Mode
0
1
x
Figure 29
Note 40. If M/S bit = “1”, PMPLL bit = “0” and MCKO bit = “1” during the setting of PLL Master Mode, the invalid
clocks are output from MCKO pin when MCKO bit is “1”.
Table 2. Clock Mode Setting (x: Don’t care)
Mode
PLL Master Mode
PLL Slave Mode
(PLL Reference Clock: MCKI pin)
MCKO bit
0
1
0
1
MCKO pin
L
Selected by
PS1-0 bits
L
Selected by
PS1-0 bits
MCKI pin
Selected by
PLL3-0 bits
Selected by
PLL3-0 bits
PLL Slave Mode
(PLL Reference Clock: LRCK or BICK pin)
0
L
GND
EXT Slave Mode
0
L
Selected by
FS1-0 bits
EXT Master Mode
0
L
Selected by
FS1-0 bits
Table 3. Clock pins state in Clock Mode
BICK pin
Output
(Selected by
BCKO bit)
Input
(≥ 32fs)
Input
(Selected by
PLL3-0 bits)
Input
(≥ 32fs)
Output
(Selected by
BCKO bit)
LRCK pin
Output
(1fs)
Input
(1fs)
Input
(1fs)
Input
(1fs)
Output
(1fs)
■ Master Mode/Slave Mode
The M/S bit selects either master or slave mode. M/S bit = “1” selects master mode and “0” selects slave mode. When the
AK4373 is power-down mode (PDN pin = “L”) and exits reset state, the AK4373 is slave mode. After exiting reset state,
the AK4373 goes to master mode by changing M/S bit = “1”.
When the AK4373 is in master mode, LRCK and BICK pins are a floating state until M/S bit becomes “1”. LRCK and
BICK pins of the AK4373 should be pulled-down or pulled-up by a resistor (about 100kΩ) externally to avoid the
floating state.
M/S bit
Mode
0
Slave Mode
(default)
1
Master Mode
Table 4. Select Master/Slave Mode
MS0991-E-00
- 29 -
2008/09