XC2V4000 Datasheet, PDF (92/311 Pages) Xilinx, Inc – Summary of Features

R
Table 5: CS144 — XC2V40, XC2V80, and XC2V250
Bank
Pin Description
2
IO_L96N_2
2
IO_L96P_2
3
IO_L96N_3
3
IO_L96P_3
3
IO_L94N_3
3
IO_L94P_3
3
IO_L03N_3/VREF_3
3
IO_L03P_3
3
IO_L02N_3/VRP_3
3
IO_L02P_3/VRN_3
3
IO_L01N_3
3
IO_L01P_3
4
IO_L01N_4/BUSY/DOUT ⁽¹⁾
4
IO_L01P_4/INIT_B
4
IO_L02N_4/D0/DIN⁽¹⁾
4
IO_L02P_4/D1
4
IO_L03N_4/D2/ALT_VRP_4
4
IO_L03P_4/D3/ALT_VRN_4
4
IO_L94N_4/VREF_4
4
IO_L94P_4
4
IO_L95N_4/GCLK3S
4
IO_L95P_4/GCLK2P
4
IO_L96N_4/GCLK1S
4
IO_L96P_4/GCLK0P
5
IO_L96N_5/GCLK7S
5
IO_L96P_5/GCLK6P
5
IO_L95N_5/GCLK5S
5
IO_L95P_5/GCLK4P
5
IO_L94N_5
5
IO_L94P_5/VREF_5
5
IO_L03N_5/D4/ALT_VRP_5
5
IO_L03P_5/D5/ALT_VRN_5
5
IO_L02N_5/D6
5
IO_L02P_5/D7
5
IO_L01N_5/RDWR_B
5
IO_L01P_5/CS_B
Virtex™-II Platform FPGAs: Pinout Information
Pin Number
G11
G13
G12
H12
H11
J13
J10
K13
K12
K11
K10
L13
M11
N11
L10
M10
N10
K9
N9
K8
L8
M8
N8
K7
N7
M7
N6
M6
L6
K6
L5
K5
N4
M4
L4
K4
No Connect in the XC2V40
DS031-4 (v2.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
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