XC2V4000 Datasheet, PDF (33/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: Detailed Description
Control Pins and Attributes
Virtex-II SelectRAM memory has two independent ports
with the control signals described in Table 16. All control
inputs including the clock have an optional inversion.
Table 16: Control Functions
Control Signal
Function
CLK
Read and Write Clock
EN
Enable affects Read, Write, Set, Reset
WE
Write Enable
SSR
Set DO register to SRVAL (attribute)
Initial memory content is determined by the INIT_xx
attributes. Separate attributes determine the output register
value after device configuration (INIT) and SSR is asserted
(SRVAL). Both attributes (INIT_B and SRVAL) are available
for each port when a block SelectRAM resource is config-
ured as dual-port RAM.
Locations
Virtex-II SelectRAM memory blocks are located in either
four or six columns. The number of blocks per column
depends of the device array size and is equivalent to the
number of CLBs in a column divided by four. Column loca-
tions are shown in Table 17.
Table 17: SelectRAM Memory Floor Plan
SelectRAM Blocks
Device
Columns Per Column
Total
XC2V40
2
2
4
XC2V80
2
4
8
XC2V250
4
6
24
XC2V500
4
8
32
XC2V1000
4
10
40
XC2V1500
4
12
48
XC2V2000
4
14
56
XC2V3000
6
16
96
XC2V4000
6
20
120
XC2V6000
6
24
144
XC2V8000
6
28
168
SelectRAM Blocks
SelectRAM Blocks
SelectRAM Blocks
ds031_38_101000
Figure 34: Block SelectRAM (2-column, 4-column, and 6-column)
DS031-2 (v3.0) August 1, 2003
Product Specification
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