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XC2V4000 Datasheet, PDF (82/311 Pages) Xilinx, Inc – Summary of Features
R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Source-Synchronous Switching Characteristics
The parameters in this section provide the necessary values for calculating timing budgets for Virtex-II source-synchronous
transmitter and receiver data-valid windows.
Table 41: Duty Cycle Distortion and Clock-Tree Skew
Speed Grade
Description
Duty Cycle Distortion(1)
Clock Tree Skew(2)
Symbol
TDCD_CLK0
TDCD_CLK180
TCKSKEW
Device
–6
–5
–4
Units
All
140
140
140
ps
All
50
50
50
ps
XC2V40
TBD
50
TBD
ps
XC2V80
TBD
50
TBD
ps
XC2V250
TBD
50
TBD
ps
XC2V500
TBD
50
TBD
ps
XC2V1000
TBD
80
TBD
ps
XC2V1500
TBD
80
TBD
ps
XC2V2000
TBD
100
TBD
ps
XC2V3000
TBD
100
TBD
ps
XC2V4000
TBD
TBD
TBD
ps
XC2V6000
TBD
500
TBD
ps
XC2V8000
TBD
TBD
TBD
ps
Notes:
1. These parameters represent the worst-case duty cycle distortion observable at the pins of the device using LVDS output buffers. For
cases where other I/O standards are used, IBIS can be used to calculate any additional duty cycle distortion that might be caused
by asymmetrical rise/fall times.
TDCD_CLK0 applies to cases where local (IOB) inversion is used to provide the negative-edge clock to the DDR element in the I/O.
TDCD_CLK180 applies to cases where the CLK180 output of the DCM is used to provide the negative-edge clock to the DDR element
in the I/O.
2. This value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew
exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx FPGA_Editor
and Timing Analyzer tools to evaluate clock skew specific to your application.
Table 42: Package Skew
Description
Symbol
Device/Package
Value Units
Package Skew(1)
TPKGSKEW
XC2V1000 / FF896
XC2V3000 / FF1152
130
ps
115
ps
XC2V3000 / BF957
130
ps
XC2V4000 / FF1152
130
ps
XC2V4000 / FF1517
200
ps
XC2V4000 / BF957
140
ps
XC2V6000 / FF1152
90
ps
XC2V6000 / FF1517
105
ps
XC2V6000 / BF957
105
ps
Notes:
1. These values represent the worst-case skew between any two balls of the package: shortest flight time to longest flight time from Pad
to Ball (7.1ps per mm).
2. Package trace length information is available for these device/package combinations. This information can be used to deskew the
package.
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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