XC2V4000 Datasheet, PDF (208/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: Pinout Information
Table 12: FF1152 BGA — XC2V3000, XC2V4000, XC2V6000, and XC2V8000
Bank
Pin Description
Pin Number
0
IO_L75P_0/VREF_0
F20
0
IO_L76N_0
B21
0
IO_L76P_0
B22
0
IO_L77N_0
J20
0
IO_L77P_0
K19
0
IO_L78N_0
D20
0
IO_L78P_0
D21
0
IO_L79N_0
A21
0
IO_L79P_0
A22
0
IO_L80N_0
L19
0
IO_L80P_0
L18
0
IO_L81N_0
B19
0
IO_L81P_0/VREF_0
A20
0
IO_L82N_0
A18
0
IO_L82P_0
B18
0
IO_L83N_0
H19
0
IO_L83P_0
H18
0
IO_L84N_0
C20
0
IO_L84P_0
C21
0
IO_L91N_0/VREF_0
D19
0
IO_L91P_0
D18
0
IO_L92N_0
G18
0
IO_L92P_0
G19
0
IO_L93N_0
F18
0
IO_L93P_0
F19
0
IO_L94N_0/VREF_0
C19
0
IO_L94P_0
C18
0
IO_L95N_0/GCLK7P
K18
0
IO_L95P_0/GCLK6S
J18
0
IO_L96N_0/GCLK5P
E19
0
IO_L96P_0/GCLK4S
E18
No Connect in the XC2V3000
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
1
IO_L96N_1/GCLK3P
E17
1
IO_L96P_1/GCLK2S
E16
1
IO_L95N_1/GCLK1P
H17
1
IO_L95P_1/GCLK0S
H16
DS031-4 (v2.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
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