XC2V4000 Datasheet, PDF (73/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: DC and Switching Characteristics
Block SelectRAM Switching Characteristics
Table 27: Block SelectRAM Switching Characteristics
Description
Sequential Delays
Clock CLK to DOUT output
Setup and Hold Times Before Clock CLK
ADDR inputs
DIN inputs
EN input
RST input
WEN input
Clock CLK
Minimum Pulse Width, High
Minimum Pulse Width, Low
Symbol
T_BCKO
T_BACK/T_BCKA
T_BDCK/T_BCKD
T_BECK/T_BCKE
T_BRCK/T_BCKR
T_BWCK/T_BCKW
T_BPWH
T_BPWL
Speed Grade
–6
–5
–4
2.10
2.31
2.65
0.29/ 0.00
0.29/ 0.00
0.95/–0.46
1.31/–0.71
0.57/–0.19
0.32/ 0.00
0.32/ 0.00
1.04/–0.50
1.44/–0.78
0.63/–0.21
0.36/ 0.00
0.36/ 0.00
1.20/–0.58
1.65/–0.90
0.72/–0.25
1.17
1.29
1.48
1.17
1.29
1.48
Units
ns, Max
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
ns, Min
TBUF Switching Characteristics
Table 28: TBUF Switching Characteristics
Description
Combinatorial Delays
IN input to OUT output
TRI input to OUT output high-impedance
TRI input to valid data on OUT output
Symbol
Speed Grade
–6
–5
–4
Units
T_IO
T_OFF
T_ON
0.45 0.50 0.58
0.44 0.48 0.55
0.44 0.48 0.55
ns, Max
ns, Max
ns, Max
JTAG Test Access Port Switching Characteristics
Table 29: JTAG Test Access Port Switching Characteristics
Description
TMS and TDI Setup times before TCK
TMS and TDI Hold times after TCK
Output delay from clock TCK to output TDO
Maximum TCK clock frequency
Symbol
T_TAPTK
T_TCKTAP
T_TCKTDO
F_TCK
Units
5.5
ns, Min
0.0
ns, Min
10.0
ns, Max
33
MHz, Max
DS031-3 (v3.0) August 1, 2003
Product Specification
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