XC2V4000 Datasheet, PDF (9/311 Pages) Xilinx, Inc – Summary of Features

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Virtex™-II Platform FPGAs:
Detailed Description
DS031-2 (v3.0) August 1, 2003
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Detailed Description
Input/Output Blocks (IOBs)
Virtex-II I/O blocks (IOBs) are provided in groups of two or
four on the perimeter of each device. Each IOB can be used
as input and/or output for single-ended I/Os. Two IOBs can
be used as a differential pair. A differential pair is always
connected to the same switch matrix, as shown in Figure 1.
IOB blocks are designed for high performances I/Os, sup-
porting 19 single-ended standards, as well as differential
signaling with LVDS, LDT, Bus LVDS, and LVPECL.
Switch
Matrix
IOB
PAD4
IOB
PAD3
IOB
PAD2
IOB
PAD1
Differential Pair
Differential Pair
DS031_30_101600
Figure 1: Virtex-II Input/Output Tile
Note: Differential I/Os must use the same clock.
Supported I/O Standards
Virtex-II IOB blocks feature SelectI/O-Ultra inputs and out-
puts that support a wide variety of I/O signaling standards.
In addition to the internal supply voltage (VCCINT = 1.5V),
output driver supply voltage (VCCO) is dependent on the
I/O standard (see Table 1). An auxiliary supply voltage
(VCCAUX = 3.3 V) is required, regardless of the I/O stan-
dard used. For exact supply voltage absolute maximum rat-
ings, see DC Input and Output Levels in Module 3.
Product Specification
Table 1: Supported Single-Ended I/O Standards
I/O
Standard
Output
V_CCO
Input
V_CCO
Input
V_REF
Board
Termination
Voltage (V_TT)
LVTTL
3.3
3.3
N/A
N/A
LVCMOS33
3.3
3.3
N/A
N/A
LVCMOS25
2.5
2.5
N/A
N/A
LVCMOS18
1.8
1.8
N/A
N/A
LVCMOS15
1.5
1.5
N/A
N/A
PCI33_3
3.3
3.3
N/A
N/A
PCI66_3
3.3
3.3
N/A
N/A
PCI-X
3.3
3.3
N/A
N/A
GTL
Note (1) Note (1) 0.8
1.2
GTLP
Note (1) Note (1) 1.0
1.5
HSTL_I
1.5
N/A
0.75
0.75
HSTL_II
1.5
N/A
0.75
0.75
HSTL_III
1.5
N/A
0.9
1.5
HSTL_IV
1.5
N/A
0.9
1.5
HSTL_I
1.8
N/A
0.9
0.9
HSTL_II
1.8
N/A
0.9
0.9
HSTL_III
1.8
N/A
1.1
1.8
HSTL_IV
1.8
N/A
1.1
1.8
SSTL2_I
2.5
N/A
1.25
1.25
SSTL2_II
2.5
N/A
1.25
1.25
SSTL3_I
3.3
N/A
1.5
1.5
SSTL3_II
3.3
N/A
1.5
1.5
AGP-2X/AGP 3.3
N/A
1.32
N/A
Notes:
1. V_CCO of GTL or GTLP should not be lower than the
termination voltage or the voltage seen at the I/O pad.
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DS031-2 (v3.0) August 1, 2003
Product Specification
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