XC2V4000 Datasheet, PDF (311/311 Pages) Xilinx, Inc – Summary of Features

R
Virtex™-II Platform FPGAs: Pinout Information
Revision History
This section records the change history for this module of the data sheet.
Date
11/07/00
11/22/00
12/19/00
01/25/01
02/07/01
04/02/01
11/07/01
09/26/02
10/07/02
12/06/02
05/07/03
06/19/03
08/01/03
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
1.7
1.8
1.8.1
1.8.2
1.8.3
2.0
Revision
Early access draft.
Initial Xilinx release. Made the following corrections:
CS144 package - Table 5, page 5:
• Added missing pin D10 in Bank 1.
• Changed dedicated pins A2 and B2 to RSVD (from DXN and DXP).
FG256 package - Table 6, page 10:
• Changed dedicated pins A3 and A4 to RSVD (from DXN and DXP).
FG896 package - Table 11, page 94:
• Corrected pin AG1 in Bank 4 to be AG12.
FF1152 package - Table 12, page 120:
• Corrected pin Y3 in Bank 6 to be Y32.
Reverse designations were fixed for pins in every package.
The data sheet was divided into four modules (per the current style standard). DXN and
DXP pin information was added for the CS144 package (Table 5) and the FG256 package
(Table 6).
DXN and DXP pin information was changed back to RSVD for the CS144 package (Table 5)
and the FG256 package (Table 6).
• ALT_VRN and ALT_VRP pin information was added for each package.
• Table 8, page 34 – added No Connect designations for the XC2V1500 device in the
FG676 package.
• Reverted to traditional double-column format.
• Updated list of devices supported in the FF1152, FF1517, and BF957 packages.
• Updated Table 3 to reflect devices supported in the BG728 and BF957 packages.
• Added mention of LVPECL to pin definition in Table 4.
• Corrected Table 10 heading to reflect supported devices in the BG728 package.
• Enhanced the description of the PWRDWN_B pin in Table 4.
• Added clarification to Table 4 and all device pinout tables regarding the dual-use
nature of pins D0/DIN and BUSY/DOUT during configuration.
• The final GND pin in each of five pinout tables was inadvertently deleted in v1.8.2. This
revision restores the deleted GND pins as follows:
- Pin C5, Table 5, page 5 (CS144)
- Pin A1, Table 6, page 10 (FG256)
- Pin A2, Table 10, page 72 (BG728)
- Pin A2, Table 12, page 120 (FF1152)
- Pin AL30, Table 14, page 198 (BF957)
All Virtex-II devices and speed grades now Production. See Table 13, Module 3.
Virtex-II Data Sheet
The Virtex-II Data Sheet contains the following modules:
• Virtex™-II Platform FPGAs: Introduction and Overview
(Module 1)
• Virtex™-II Platform FPGAs: Detailed Description
(Module 2)
• Virtex™-II Platform FPGAs: DC and Switching
Characteristics (Module 3)
• Virtex™-II Platform FPGAs: Pinout Information
(Module 4)
DS031-4 (v2.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 4 of 4
225