 English |
|
|
|
|
|
|
|
| XC2V4000 Datasheet, PDF (65/311 Pages) Xilinx, Inc – Summary of Features | |||
| |||
| ◁ |
R
Virtexâ¢-II Platform FPGAs: DC and Switching Characteristics
Table 18: Delay Measurement Methodology
Standard
VL(1)
LVTTL
0
VH(1)
3
Meas. Point
1.4
LVCMOS33
0
3.3
1.65
LVCMOS25
0
2.5
1.25
LVCMOS18
0
1.8
0.9
LVCMOS15
0
1.5
0.75
PCI33_3
Per PCI Specification
PCI66_3
Per PCI Specification
PCIX33_3
Per PCIâX Specification
GTL
GTLP
HSTL Class I
HSTL Class II
HSTL Class III
HSTL Class IV
SSTL3 I & II
SSTL2 I & II
AGP
LVDS_25
VREF â 0.2
VREF â 0.2
VREF â 0.5
VREF â 0.5
VREF â 0.5
VREF â 0.5
VREF â 1.0
VREF â 0.75
VREF â (0.2xVCCO)
1.2 â 0.125
VREF + 0.2
VREF + 0.2
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 0.5
VREF + 1.0
VREF + 0.75
VREF + (0.2xVCCO)
1.2 + 0.125
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
VREF
1.2
LVDS_33
1.2 â 0.125
1.2 + 0.125
1.2
LVDSEXT_25
1.2 â 0.125
1.2 + 0.125
1.2
LVDSEXT_33
1.2 â 0.125
1.2 + 0.125
1.2
ULVDS_25
0.6 â 0.125
0.6 + 0.125
0.6
LDT_25
0.6 â 0.125
0.6 + 0.125
0.6
LVPECL
1.6 â0.3
1.6 + 0.3
1.6
Notes:
1. Input waveform switches between VLand VH.
2. Measurements are made at VREF (Typ), Maximum, and Minimum. Worst-case values are reported.
VREF (Typ)(2)
â
â
â
â
â
â
â
â
0.80
1.0
0.75
0.75
0.90
0.90
1.5
1.25
Per AGP Spec
DS031-3 (v3.0) August 1, 2003
Product Specification
www.xilinx.com
1-800-255-7778
Module 3 of 4
17
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese